Semiconductor thin film forming method, production methods for semiconductor device and electrooptical device, devices used for these methods, and semiconductor device and electrooptical device

ABSTRACT

An object of the present invention is to provide a method for easily forming a polycrystalline semiconductor thin-film, such as polycrystalline silicon having high crystallinity and high quality, or a single crystalline semiconductor thin-film at inexpensive cost, the crystalline semiconductor thin-film having a large area, and to provide an apparatus for processing the method described above. In forming a polycrystalline (or single crystalline) semiconductor thin-film ( 7 ), such as a polycrystalline silicon thin-film, having high crystallinity and a large grain size on a substrate ( 1 ), or in forming a semiconductor device having the polycrystalline (or single crystalline) semiconductor thin-film ( 7 ) on the substrate ( 1 ), a method comprises forming a low-crystallization semiconductor thin-film ( 7 A) on the substrate ( 1 ), and subsequently heating and cooling this low-crystallization semiconductor thin-film ( 7 A) to a fusion, a semi-fusion, or a non-fusion state by flash lamp annealing to facilitate the crystallization of the low-crystallization semiconductor thin-film, whereby a polycrystalline (single crystalline) semiconductor thin-film ( 7 ) is obtained. A method for forming the semiconductor device and an apparatus for processing the methods are also disclosed.

TECHNICAL FIELD

[0001] The present invention relates to methods and apparatuses forgrowing polycrystalline or a single crystalline semiconductor thin-film,such as polycrystalline silicon, single crystalline silicon, or thelike, on a substrate, to methods and apparatuses for manufacturingsemiconductor devices and electrooptic devices having thepolycrystalline or the single crystalline semiconductor thin-film on thesubstrate, and to the semiconductor devices and the electroopticdevices.

BACKGROUND ART

[0002] Heretofore, when a source, a drain, and a channel region of aMOSFET (Metal-Oxide-Semiconductor Field Effect Transistor),such as aMOSTFT (Thin Film Transistor=thin-film insulating gate type field effecttransistor) are formed, vapor-phase growth, such as plasma CVD (CVD:Chemical Vapor Deposition), reduced-pressure CVD, or catalytic CVD,solid-phase growth, liquid-phase growth, excimer laser anneal, and thelike have been used.

[0003] As disclosed in Japanese Unexamined Patent ApplicationPublication Nos. 7-131030 and 9-116156, and Japanese Examined PatentApplication Publication No. 7-118443, by simply performinghigh-temperature anneal or excimer laser anneal (ELA) for amorphous ormicrocrystalline silicon films formed by plasma CVD, reduced-pressureCVD, or the like to form polycrystalline silicon films, improvement incarrier mobility has been performed: however, according to this method,a carrier mobility of approximately up to 80 to 120 cm²/V·sec has beenonly obtained.

[0004] However, since the electron mobility of a MOSFET using apolycrystalline silicon film obtained by performing ELA for an amorphoussilicon-film formed by plasma CVD is approximately 100 cm²/V·sec, andhigher integration density can also be satisfied, in recent years, anLCD (Liquid Crystal Device) which uses polycrystalline silicon MOSTFTsand which is integrated with driving circuits has attracted attention(see Japanese Unexamined Patent Application Publication No. 6-242433).By using excimer laser annealing which is a method for performing fusionand crystallization by irradiating a sample with short wavelength andshort pulse laser such as XeCl excimer laser, polycrystallization ofamorphous silicon films can be-performed by laser light emission withoutdamaging glass substrates, and high throughput can be expected.

[0005] However, according to the above method for manufacturing thepolycrystalline MOSFET using ELA, since crystallization speed is high inthe order of nanoseconds, the diameter of obtained crystal grains isapproximately up to 100 nm. As a result, even when a method is performedin which substrate temperature is heated to approximately 400° C. whileshort wavelength and short pulse laser is emitted, and in whichhydrogen, oxygen, and the like which inhibit the crystal growth aresufficiently removed so as to control the solidification speed, it hasbeen difficult to obtain crystals having a grain size of 500 nm or more.Accordingly, energy sufficient to grow crystals has been given byperforming laser emission at least two times, such as 5 times or 30times or more, so as to form polycrystalline silicon films having alarge grain size. However, there have been a number of problems, such asunstable excimer laser output, poor productivity, increase in cost ofapparatus due to increased size thereof, lower yield, degradation inquality, and the like, and in particular, when a large glass substratehaving a size of 1 meter by 1 meter is used, the problems mentionedabove become more serious, and as a result, it becomes more difficult toimprove performance and quality and to reduce cost.

[0006] In recent years, in Japanese Unexamined Patent ApplicationPublication No. 11-97353, a method has been proposed in which acatalytic element (Ni, Fe, Co, or the like) which facilitatescrystallization is diffused in an amorphous silicon film by heattreatment at 450 to 600° C. for 4 to 12 hours so as to form acrystalline silicon film. However, according to this method, since thecatalytic element remains in the crystalline silicon film thus formed,in order to remove (gettering) this catalytic element, as disclosed inJapanese Unexamined Patent Application Publication No. 8-339960, therehave been proposed a method for performing heat treatment in anatmosphere containing halogen elements such as chlorine; a method forselectively adding phosphorus to a crystalline silicon film and thenperforming heat treatment; and after a crystalline silicon filmcontaining a catalytic element is irradiated with laser light orintensive light to allow the catalytic element to diffuse easily, amethod for absorbing the catalytic element by an element which isselectively added. However, the process is complicated, sufficientgettering effect cannot be obtained, semiconductor properties of thesilicon film are degraded, and the stability and the reliability ofelements thus formed are degraded.

[0007] In addition, according to a method for manufacturing apolycrystalline silicon MOSTFT by a solid-state growth, since annealingat 600° C. or more for ten and several hours and formation of a gateSiO₂ by thermal oxidation at approximately 1,000° C. must be performed,semiconductor device manufacturing equipment must be used. Accordingly,the substrate size is up to a wafer size of 8 to 12 inches in diameter,and a synthetic quartz glass which is expensive and which is heatresistance must be used. Hence, it is difficult to reduce cost, and theapplications are limited to EVF and data/AV projectors.

[0008] Recently, a catalytic CVD method which is a thermal CVD methodcapable of forming a polycrystalline silicon film, a silicon nitridefilm, or the like on an insulating substrate such as a glass substrateat a low temperature has been developed (see Japanese Examined PatentApplication Publication Nos. 63-41314 and 8-250438), and studies forpractical use thereof has been actively performed. In a catalytic CVDmethod, without performing anneal for crystallization, a carriermobility of approximately 30 cm²/V·sec has been obtained; however, thevalue mentioned above is not large enough to manufacture superiorMOSTFTs. In addition, when a polycrystalline silicon film is formed on aglass substrate, amorphous silicon in an initial transition state (athickness of 5 to 10 nm) may be easily formed depending on film-formingconditions, and when a bottom-gate MOSTFT is formed, it is difficult toobtain desired carrier mobility. In general, in an LCD which usespolycrystalline silicon MOSTFTs and which is integrated with drivingcircuits, bottom-gate MOSTFTs are preferably formed in view of yield andproductivity; however, the problem described above has been stillserious.

[0009] An object of the present invention is to provide a method foreasily forming a polycrystalline or a single crystalline semiconductorthin-film, such as polycrystalline silicon or the like, having highcrystallinity, superior quality, and a large area at low cost, and toprovide an apparatus for performing the method described above.

[0010] Another object of the present invention is to provide a methodfor manufacturing a semiconductor device, such as MOSTFT, having thepolycrystalline or the single crystalline semiconductor thin-filmdescribed above as a constituent element; a method for manufacturing anelectrooptic device; apparatuses for performing the methods mentionedabove; and the semiconductor device and the electrooptic device.

DISCLOSURE OF INVENTION

[0011] In forming a polycrystalline or a single crystallinesemiconductor thin-film on a substrate, or in forming a semiconductordevice having a polycrystalline or a single crystalline semiconductorthin-film on a substrate, a method for forming a semiconductor thin-filmor for manufacturing a semiconductor device, according to the presentinvention, comprises a first step of forming a low-crystallizationsemiconductor thin-film on the substrate, and a second step of heatingand cooling the low-crystallization semiconductor thin-film to a fusion,a semi-fusion, or a non-fusion state by flash lamp annealing tofacilitate the crystallization of the low-crystallization semiconductorthin-film.

[0012] In addition, as an apparatus for performing the method of thepresent invention, the present invention provides a forming apparatusfor forming a polycrystalline or a single crystalline semiconductorthin-film or a manufacturing apparatus for manufacturing a semiconductordevice, in which the apparatus comprises first means for forming alow-crystallization semiconductor thin-film on the substrate, and secondmeans for heating and cooling the low-crystallization semiconductorthin-film to a fusion, a semi-fusion, or a non-fusion state by flashlamp annealing to facilitate the crystallization of thelow-crystallization semiconductor thin-film.

[0013] In addition, the present invention provides an electroopticdevice which comprises a cathode or an anode, which is provided undereach of organic or inorganic electroluminescent layers for individualcolors and which is connected to a drain or a source of a MOSTFTcomposed of the polycrystalline or the single crystalline semiconductorthin-film, wherein active elements including the MOSTFT and a diode arecovered with the cathode, or the cathode or the anode is provided on andbetween the organic or the inorganic electroluminescent layers forindividual colors so as to cover the entire surface.

[0014] In addition, the present invention also provides an electroopticdevice in which each emitter of a field emission display (FED) device isconnected to a drain of a MOSTFT formed of the polycrystalline or thesingle crystalline semiconductor thin-film via the polycrystalline orthe single crystalline semiconductor thin-film and is formed of ann-type polycrystalline semiconductor film, a polycrystalline diamondfilm, a carbon thin-film which may or may not contain nitrogen, a numberof protruding structures (for example, carbon nanotube) formed on asurface of a carbon thin-film which may or may not contain nitrogen, orthe like, which is formed on the polycrystalline or the singlecrystalline semiconductor thin-film.

[0015] According to the present invention, since a polycrystalline or asingle crystalline semiconductor thin-film is formed by forming alow-crystallization semiconductor thin-film on a substrate andsubsequently by heating and cooling the low-crystallizationsemiconductor thin-film to a fusion, a semi-fusion, or a non-fusionstate by flash lamp annealing to facilitate the crystallization of thelow-crystallization semiconductor thin-film, the significant advantages(1) to (10) described below can be obtained.

[0016] (1) By flash lamp annealing in which flash emission can beperformed once or repeatedly in an optional short period of time in therange of microseconds to milliseconds, high emission energy is given toa low-crystallization semiconductor thin-film such aslow-crystallization silicon so that the semiconductor thin-film isheated and cooled to a fusion, a semi-fusion state, or a non-fusionstate, and hence, a polycrystalline semiconductor thin-film such as apolycrystalline silicon thin-film having a large grain size, highcarrier mobility, and high quality, or a single crystallinesemiconductor thin-film is obtained, whereby the productivity issignificantly increased, and considerable cost reduction can berealized.

[0017] (2) In flash lamp annealing, by combining an optional number oflamps with a flash discharge mechanism therefor, for example, {circleover (1)} the entire large area of 1,000 mm×1,000 mm may besimultaneously irradiated once or repeatedly as required with flashemission light, {circle over (2)} flash emission light which iscondensed and homogenized to have a square emission area of 200 mm×200mm may be scanned by a galvanometer scanner, and when necessary, flashemission may be performed by overlap scanning, or {circle over (3)}under the conditions in which the emission position of flash emissionlight which is condensed and homogenized to have a square emission areaof 200 mm×200 mm is fixed, and a substrate is moved in a step & repeatmanner, flash emission may be performed and, when necessary, may beperformed by overlap scanning. As described above, since the substrateor flash emission light can be moved in an optional direction at anoptional speed, heating and cooling rate can be controlled, an optionallarge area of a low-crystallization silicon thin-film or the like can beconverted into a polycrystalline or a single crystalline thin-film in anextremely short time, and hence, significantly high productivity andconsiderable cost reduction can be realized.

[0018] (3) Since flash emission light is condensed and homogenized tohave an optional strip, rectangular, square, or circular form and isthen emitted, the emission intensity, that is, fusion efficiency andthroughput, is improved, and variation in carrier mobility can bedecreased by improvement in uniformity of crystallization.

[0019] (4) By repeating a method in which a low-crystallization siliconfilm or the like is formed on a polycrystalline silicon film or the likecrystallized by flash lamp annealing, and crystallization is againperformed by flash lamp annealing, a polycrystalline silicon film or thelike, which has a large grain size, high carrier mobility, and highquality, can be formed in a laminated shape having a thickness in theorder of micrometers. Accordingly, in addition to MOSLSIs, highperformance and high quality bipolar LSIs, CMOS sensors, CCD area/linearsensors, solar cells, and the like can be formed.

[0020] (5) Since adjustment of wavelength (change of an enclosed gas,change of discharge conditions, use of an IR-reducing or an IR-blockingfilter, or the like) and control of emission intensity, emission time,and the like in flash lamp annealing can be easily performed inaccordance with-the film thickness of a low-crystallizationsemiconductor thin-film, a heat resistant temperature of a substratesuch as glass, a desired grain size (carrier mobility), and the like, apolycrystalline silicon film or the like having high carrier mobilityand high quality can be reproducibly obtained at a high productivityrate.

[0021] (6) Lamps used for flash lamp annealing, such as xenon lamps,xenon-mercury lamps,-krypton lamps, krypton-mercury lamps, xenon-kryptonlamps, xenon-krypton-mercury lamps, and metal halide lamps, which canwithstand repeated light emission, are much inexpensive than an excimerlaser oscillator of an excimer laser annealing apparatus using XeCl,KrF, or the like, have a longer life, and require easier maintenance,and hence, considerable cost reduction can be achieved.

[0022] (7) Since a flash lamp annealing apparatus primarily composed offlash lamps and a discharge circuit has a simple structure compared tothat of an excimer laser annealing apparatus, it is inexpensive, andhence, cost reduction can be realized.

[0023] (8) Since excimer laser annealing performed by XeCl, KrF, or thelike uses a pulse oscillating laser in the order of nanoseconds, therehas been a problem of output stability, and hence, there have beenvariation in energy distribution in an irradiation area, variation inquality of obtained crystallized semiconductor films, and variation inelement performance between TFTs. Accordingly, a method in which excimerlaser pulse is emitted many times, such as 5 times or 30 times, isperformed while a temperature of approximately 400° C. is applied;however, properties of crystallized semiconductor films and TFT elementsvary due to the emission variation, and the cost is increased bydecrease in productivity rate caused by decrease in throughput. Incontrast, in flash lamp annealing, as described in the above (2), sincethe entire large area of, for example, 1,000 mm×1,000 mm can besimultaneously irradiated with flash emission light using a pulse in therange of microseconds to milliseconds, variation in energy distributionin the irradiation area, variation in quality of obtained crystallizedsemiconductor films, and variation in element performance between TFTsare small, and cost reduction can be realized by a high productivityrate caused by high throughput.

[0024] (9) In particular, when an IR-blocking or an IR-reducing filterwhich at least blocks or reduces infrared, such as color filter glass(IR-absorbing filter) containing an IR-absorbing material, such aspowdered copper or powdered iron; a cold mirror/cold filter coated withan infrared reflection film such as an ITO film; or a filter composed ofboth filters mentioned above (an IR-absorbing filter coated with anIR-reflecting film, or the like) is used, since flash lamp annealing byintensive ultraviolet rays can be performed at a low temperature (200 to400° C.), a low strain point glass, such as aluminosilicate glass orborosilicate glass, or a heat resistant resin such as polyimide, whichis inexpensive and can be formed into a large size, may be used, andhence, reduction in weight and cost can be achieved.

[0025] (10) In addition to a top gate type, since a polycrystallinesemiconductor film or a single crystalline semiconductor film havinghigh carrier mobility can be used for forming a bottom gate type, a dualgate type, and a back gate type MOSTFTs, for example, high speed, highcurrent density semiconductor devices, electrooptic devices, and highlyefficient solar cells can be formed using this high performancesemiconductor films. For example, there may be mentioned siliconsemiconductor devices, silicon semiconductor integrated circuit devices,field emission display (FED) devices, silicon-germanium semiconductordevices, silicon-germanium semiconductor integrated circuit devices,silicon carbide semiconductor devices, silicon carbide semiconductorintegrated circuit devices, III-V and II-VI compound semiconductordevices, III-V and II-VI compound semiconductor integrated circuitdevices, polycrystalline or single crystalline diamond semiconductordevices, polycrystalline or single crystalline diamond semiconductorintegrated circuit devices, liquid crystal display devices,electroluminescent (organic or inorganic) display devices,light-emitting polymer display devices, light-emitting diode displaydevices, light sensor devices, CCD area/linear sensor devices, CMOSsensor devices, and solar cells.

[0026] In the present invention, as defined later, thelow-crystallization semiconductor thin-film described above primarilyhas the structure primarily composed of an amorphous material, amicrocrystalline material (generally having a grain size of 10 nm orless), an amorphous material containing a microcrystalline component, amicrocrystalline material containing an amorphous component, or apolycrystalline material containing amorphous and microcrystallinecomponents, and the polycrystalline semiconductor thin-film describedabove is obtained by removing the amorphous component from the abovelow-crystallization semiconductor thin-film and has the structureprimarily composed of a polycrystalline material having a large grainsize (generally, the grain size is several hundred nanometers or more)and also containing a microcrystalline component. In addition to singlecrystalline semiconductor such as single crystalline silicon, the singlecrystalline semiconductor thin-film described above is a conceptincluding single crystalline compound semiconductor (such as singlecrystalline gallium arsenide) and single crystalline silicon-germanium,and the single crystal is defined as a concept including a singlecrystal containing subgrains or transformation. Furthermore, thepolycrystalline diamond film described above is defined as a crystallinediamond film which does not substantially contain amorphous diamond butmicrocrystalline and polycrystalline diamond.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 includes cross-sectional views of a process formanufacturing a MOSTFT sequentially shown by steps according to a firstembodiment of the present invention.

[0028]FIG. 2 includes cross-sectional views of the manufacturing processsequentially shown by steps according to the first embodiment.

[0029]FIG. 3 includes cross-sectional views of the manufacturing processsequentially shown by steps according to the first embodiment.

[0030]FIG. 4 includes cross-sectional views of the manufacturing processsequentially shown by steps according to the first embodiment.

[0031]FIG. 5 is a schematic cross-sectional view of a catalytic CVDapparatus, which is placed in one state, used for manufacturingaccording to the first embodiment.

[0032]FIG. 6 is a schematic cross-sectional view of the apparatus, whichis placed in another state, according to the first embodiment.

[0033]FIG. 7 is a schematic cross-sectional view of a flash lampannealing apparatus according to the first embodiment.

[0034]FIG. 8 is a graph showing spectral properties of the flash lampaccording to the first embodiment.

[0035]FIG. 9 includes schematic cross-sectional views of a part of theflash lamp annealing apparatus according to the first embodiment.

[0036]FIG. 10 includes schematic cross-sectional views, side views, andplan views of various flash lamp annealing apparatuses according to thefirst embodiment.

[0037]FIG. 11 includes a schematic cross-sectional view and a plan viewshowing another example of a flash lamp annealing apparatus according tothe first embodiment.

[0038]FIG. 12 includes schematic views of various flash lamps accordingto the first embodiment.

[0039]FIG. 13 includes front views and a plan view showing examples offlash lamps provided with a trigger electrode according to the firstembodiment.

[0040]FIG. 14 is a schematic view of a cluster type apparatus formanufacturing a MOSTFT according to the first embodiment.

[0041]FIG. 15 includes schematic views of in-line type apparatuses formanufacturing a MOSTFT according to the first embodiment.

[0042]FIG. 16 is a schematic view showing another example of a clustertype apparatus for manufacturing a MOSTFT according to the firstembodiment.

[0043]FIG. 17 includes a schematic cross-sectional view and a plan viewshowing another example of a flash lamp annealing apparatus according tothe first embodiment.

[0044]FIG. 18 includes a view and a graph for illustrating one flashemission mode of flash lamp annealing according to the first embodiment.

[0045]FIG. 19 is a graph for illustrating another mode according to thefirst embodiment.

[0046]FIG. 20 is a graph showing various discharge current waveforms inflash emission according to the first embodiment.

[0047]FIG. 21 is a graph showing another mode according to the firstembodiment.

[0048]FIG. 22 is a graph showing still another mode according to thefirst embodiment.

[0049]FIG. 23 is an equivalent circuit diagram of a charge and dischargecircuit of the flash lamp according to the first embodiment.

[0050]FIG. 24 includes cross-sectional views showing another mode inflash lamp annealing according to the first embodiment.

[0051]FIG. 25 is a SEM photograph of sample A according to the firstembodiment.

[0052]FIG. 26 is a SEM photograph of sample B according to the firstembodiment.

[0053]FIG. 27 is a SEM photograph of sample C according to the firstembodiment.

[0054]FIG. 28 is a Raman spectrum of sample A according to the firstembodiment.

[0055]FIG. 29 is a Raman spectrum of sample B according to the firstembodiment.

[0056]FIG. 30 is a Raman spectrum of sample C according to the firstembodiment.

[0057]FIG. 31 includes schematic cross-sectional views showing anotherexample of a flash lamp annealing apparatus according to the firstembodiment.

[0058]FIG. 32 is a schematic cross-sectional view showing anotherexample of a flash lamp annealing apparatus according to the firstembodiment.

[0059]FIG. 33 is a schematic cross-sectional view showing anotherexample of a flash lamp annealing apparatus according to the firstembodiment.

[0060]FIG. 34 includes cross-sectional views of a process formanufacturing an LCD sequentially shown by steps according to a secondembodiment of the present invention.

[0061]FIG. 35 includes cross-sectional views of the manufacturingprocess sequentially shown by steps according to the second embodiment.

[0062]FIG. 36 includes cross-sectional views of the manufacturingprocess sequentially shown by steps according to the second embodiment.

[0063]FIG. 37 is a perspective view schematically showing the structureof the entire LCD according to the second embodiment.

[0064]FIG. 38 is an equivalent circuit diagram of the LCD according tothe second embodiment.

[0065]FIG. 39 includes cross-sectional views of another process formanufacturing an LCD sequentially shown by steps according to the secondembodiment.

[0066]FIG. 40 includes cross-sectional views of the manufacturingprocess sequentially shown by steps according to the second embodiment.

[0067]FIG. 41 includes cross-sectional views showing various MOSTFTs ofthe LCD according to the second embodiment.

[0068]FIG. 42 includes cross-sectional views of another process formanufacturing an LCD sequentially shown by steps according to the secondembodiment.

[0069]FIG. 43 includes schematic views for illustrating graphoepitaxialgrowth according to the second embodiment.

[0070]FIG. 44 includes schematic cross-sectional views showing variousstep shapes according to the second embodiment.

[0071]FIG. 45 includes cross-sectional views of another process formanufacturing an LCD sequentially shown by steps according to the secondembodiment.

[0072]FIG. 46 includes an equivalent circuit diagram (A) of a majorportion of an organic EL display device according to a third embodimentof the present invention, an enlarged cross-sectional view (B) of thesame major portion, and a cross-sectional view (C) showing the vicinityof a pixel of the same major portion.

[0073]FIG. 47 includes cross-sectional views of a process formanufacturing the organic EL display device sequentially shown by stepsaccording to the third embodiment.

[0074]FIG. 48 includes an equivalent circuit diagram (A) of a majorportion of another organic EL display device according to the thirdembodiment of the present invention, an enlarged cross-sectional view(B) of the same major portion, and a cross-sectional view (C) showingthe vicinity of a pixel of the same major portion.

[0075]FIG. 49 includes cross-sectional views of a process formanufacturing the organic EL display device sequentially shown by stepsaccording to the third embodiment.

[0076]FIG. 50 includes an equivalent circuit diagram (A) of a majorportion of an FED according to a fourth embodiment of the presentinvention, an enlarged cross-sectional view (B) of the same majorportion, and a schematic plan view (C) of the same major portion.

[0077]FIG. 51 includes cross-sectional views of a process formanufacturing the FED sequentially shown by steps according to thefourth embodiment.

[0078]FIG. 52 includes cross-sectional views of the manufacturingprocess sequentially shown by steps according to the fourth embodiment.

[0079]FIG. 53 includes an equivalent circuit diagram (A) of a majorportion of another FED according to the fourth embodiment of the presentinvention, an enlarged cross-sectional view (B) of the same majorportion, and a schematic plan view (C) of the same major portion.

[0080]FIG. 54 includes cross-sectional views of a process formanufacturing the FED sequentially shown by steps according to thefourth embodiment.

[0081]FIG. 55 includes cross-sectional views of the manufacturingprocess sequentially shown by steps according to the fourth embodiment.

[0082]FIG. 56 includes cross-sectional views of a process formanufacturing a solar cell sequentially shown by steps according to afifth embodiment of the present invention.

[0083]FIG. 57 is a diagram showing a sequence for heating a substrate inflash lamp annealing according to another embodiment of the presentinvention.

[0084]FIG. 58 is a cross-sectional view showing an example of anunderlying film or the like formed under a low-crystallizationsemiconductor thin-film according to said another embodiment.

[0085]FIG. 59 includes a plan view and a cross-sectional view of aMOSTFT using a single crystalline film formed from a low-crystallizationsemiconductor thin-film according to said another embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION

[0086] In the present invention, the low-crystallization semiconductorthin-film may be formed by vapor-phase growth such as catalytic CVD,plasma CVD, or the like, and as a source gas used therefor, for example,there may be mentioned silicon hydride or a derivative thereof; amixture of silicon hydride or a derivative thereof and a gas containinghydrogen, nitrogen, germanium, carbon, or tin; a mixture of siliconhydride or a derivative thereof and a gas which contains a dopantincluding a Group III or a Group V element of the periodic table; and amixture of silicon hydride or a derivative thereof, a gas containinghydrogen, nitrogen, germanium, carbon, or tin, and a dopant including aGroup III or a Group V element of the periodic table.

[0087] By using the source gases described above, thelow-crystallization semiconductor thin-film may be formed which iscomposed of an amorphous silicon film, an amorphous silicon filmcontaining microcrystalline silicon, a microcrystalline silicon(microcrystalline silicon containing amorphous silicon) film, apolycrystalline silicon film containing amorphous silicon andmicrocrystalline silicon, an amorphous germanium film, an amorphousgermanium film containing microcrystalline germanium, a microcrystallinegermanium (microcrystalline germanium containing amorphous germanium)film, a polycrystalline germanium film containing amorphous germaniumand microcrystalline germanium, an amorphous silicon germanium filmrepresented by Si_(x)Ge_(1−x) (0<x<1), an amorphous carbon film, anamorphous carbon film containing microcrystalline carbon, amicrocrystalline carbon (microcrystalline carbon containing amorphouscarbon) film, a polycrystalline carbon film containing amorphous carbonand microcrystalline carbon, an amorphous silicon carbide filmrepresented by Si_(x)C_(1−x) (0<x<1), or an amorphous gallium arsenidefilm represented by Ga_(x)As_(1−x) (0<x<1). This low-crystallizationsemiconductor thin-film is preferably formed of an amorphous componentas an primary component, and when a microcrystalline component iscontained, microcrystals having a grain size of 10 nm or less, whichwill be used as a seed for crystal growth, are preferably dispersed inthe thin-film.

[0088] Subsequently, during or after the growth of thislow-crystallization semiconductor thin-film, when an appropriate amount(for example, the total amount is 10¹⁷ to 10²² atoms/cc, and ispreferably 10¹⁸ to 10²⁰ atoms/cc) of at least one Group IV element, suchas tin, germanium, or lead, is added to the thin-film, and when flashlamp annealing is then preformed in the state described above,crystallization of this low-crystallization semiconductor thin-film isfacilitated when it is crystallized. In addition, for example,irregularities present at the grain boundaries in the polycrystallinesemiconductor thin-film thus formed can be decreased, film stressthereof can be decreased, and hence, a high quality polycrystallinesemiconductor thin-film having high carrier mobility can be easilyobtained. This Group IV element may be contained in thelow-crystallization semiconductor thin-film by adding to the source gasas a gas component or by using ion implantation or ion doping. Inaddition, after silicon or germanium ions are ion-implanted into amicrocrystalline semiconductor thin-film formed by reduced-pressure CVDor the like at a dose rate of, for example, 1×10¹⁵ atoms/cm² to formamorphous silicon, flash lamp annealing may be performed to form apolycrystalline silicon thin-film having a large grain size or a singlecrystalline thin-film.

[0089] Each concentration of oxygen, nitrogen, and carbon in thepolycrystalline semiconductor thin-film having a large grain size or thesingle crystalline semiconductor thin-film of the present invention is1×10¹⁹ atoms/cm² or less, or preferably 5×10¹⁸ atoms/cm² or less, andthe concentration of hydrogen is preferably 0.01 atomic percent or more.In addition, the minimum concentration region of sodium measured by SIMSis preferably 1×10¹⁸ atoms/cm² or less.

[0090] The low-crystallization semiconductor thin-film such as alow-crystallization silicon is converted into the polycrystallinesemiconductor thin-film such as a polycrystalline silicon having a largegrain size by the flash lamp annealing described above. In addition tothat, after a recess portion provided with a step having a predeterminedshape and predetermined dimensions is formed in an element-formingregion of the substrate, the low-crystallization silicon thin-film,which may or may not contain at least one Group IV element such as tin,is formed on the substrate including the recess portion described above,and the flash lamp annealing is performed so that graphoepitaxial growthoccurs using the corners of the bottom corners of the recess portion asa seed, whereby the low-crystallization silicon thin-film can beconverted into a single crystalline silicon thin-film.

[0091] Furthermore, after a material layer composed of, for example,crystalline sapphire, having good lattice matching properties withsingle crystalline silicon is formed in a predetermined element-formingregion of the substrate, the low-crystallization silicon thin-film,which may or may not contain at least one Group IV element such as tin,is formed on this material layer, and the flash lamp annealing is thenperformed so that heteroepitaxial growth occurs using the material layeras a seed, whereby the low-crystallization silicon thin-film describedabove can be converted into a single crystalline silicon thin-film. Thesurface or the like of the single crystalline silicon thin-film formedby the graphoepitaxial or the heteroepitaxial growth described above maybe processed by CMP (Chemical Mechanical Polishing) or selective etchingor the like so that a single crystalline silicon thin-film having apredetermined thickness and area is formed, the thin-film having islandsformed thereon, and when necessary, an SCSOS substrate, such as an SCSOGsubstrate, may be formed by forming a gate insulating film or aprotection film by high temperature oxidation, low temperature and highpressure annealing, or CVD. The SCSOS is single crystal semiconductor(silicon) on substrate, and the SCSOS is single crystal semiconductor(silicon) on glass.

[0092] By repeating this flash lamp annealing and the formation of thelow-crystallization semiconductor thin-film so as to form a laminate, apolycrystalline or a single crystalline semiconductor thick film in theorder of micrometers may be formed. That is, after a polycrystallinesemiconductor thin-film having a large grain size or a singlecrystalline semiconductor thin-film is formed in first flash lampannealing, on this thin-film thus formed, a low-crystallizationsemiconductor thin-film is formed and is then converted into apolycrystalline semiconductor thin-film having a large grain size or asingle crystalline semiconductor thin-film by second flash lampannealing, which is performed in a manner similar to the above, usingthe underlying polycrystalline semiconductor thin-film having a largegrain size or the single crystalline semiconductor thin-film as a seed,and the steps described above are repeated as required, thereby forminga laminate, having a thickness in the order of micrometers, composed ofthe polycrystalline semiconductor thin-films having a large grain sizeor the single crystalline semiconductor thin-films. When the laminate isformed, since lamination is sequentially performed using the underlyingpolycrystalline semiconductor thin-film having a large grain size or thesingle crystalline semiconductor thin-film as a seed, a polycrystallinesemiconductor thin-film having a large grain size or a singlecrystalline semiconductor thin-film, which is formed closer to the topsurface of the laminate, has higher crystallinity and higher purity. Inthis process, it is important to avoid the formation of low-oxidationfilms on the surface crystallized by annealing or the adhesion ofcontaminants (impurities) thereto.

[0093] In order to avoid the formation of low-oxidation films and theadhesion of contaminants, and in order to improve productivity, it ispreferable that the step of forming the low-crystallizationsemiconductor thin-film and the flash lamp annealing step becontinuously or sequentially performed in accordance with, for example,an in-line (continuous chamber) method (linear type or rotation type), amultiple chamber method, or a cluster method in an apparatus in whichmeans (plasma CVD, catalytic CVD, sputtering, or the like) and anannealer are provided.

[0094] Among those mentioned above, the cluster method (1) or (2)described below is more preferable.

[0095] (1) A cluster type integrated apparatus is an apparatus in whicha step of forming a low-crystallization semiconductor thin-film in a CVDportion, a step of crystallizing the thin-film by flash lamp annealingin an annealer portion, a step of returning the annealed thin-film tothe CVD portion, a step of forming a low-crystallization semiconductorthin-film on this annealed thin-film, and a step of crystallizing thisthin-film by flash lamp annealing in the annealer portion are repeatedlyperformed.

[0096] (2) A cluster type integrated apparatus is an apparatus in whicha step of forming a substrate-protection film (a laminate of siliconoxide and silicon nitride, or the like) in a CVD-1 portion, a step offorming a low-crystallization semiconductor thin-film in a CVD-2portion, a step of adding a Group IV element in an ion doping/ionimplanting portion when necessary, a step of crystallizing the thin-filmby flash lamp annealing in an annealer portion, and a step of forming agate insulating film (a silicon oxide film or the like) in a CVD-3portion are continuously performed.

[0097] In addition, in the steps described above, before flash lampannealing is again performed, for example, the polycrystallinesemiconductor thin-film is processed by plasma discharge using hydrogenor a hydrogen-containing gas or is processed by hydrogen-based activespecies or the like generated by a catalytic reaction (that is, byplasma or catalytic AHA (Atomic Hydrogen Anneal) treatment) so thatcleaning of the surface of the polycrystalline semiconductor thin-filmand/or removal of oxide films are performed, and after thelow-crystallization semiconductor thin-film is formed, the flash lampannealing is preferably performed. In the case described above (or alsoin another case), in particular, flash lamp annealing is preferablyperformed in a hydrogen or a hydrogen-containing gas atmosphere under areduced pressure or in a vacuum.

[0098] That is, the conditions (1) and (2) described below areparticularly preferable.

[0099] (1) Before film formation is performed by CVD, by performingplasma treatment with a hydrogen-based carrier gas or catalytic AHAtreatment without supplying source gases, contaminants (low-oxidationfilms, moisture, oxygen, nitrogen, carbon dioxide, and the like) adheredto a surface of a polycrystalline silicon thin-film formed by a firstflash lamp annealing are removed so as to clean the interface, and aremaining amorphous silicon component is etched, thereby forming apolycrystalline silicon thin-film having high crystallinity.Accordingly, by using this polycrystalline silicon thin-film as a seed,a low-crystallization silicon thin-film formed on this clean interfaceis converted into a high quality polycrystalline semiconductor thin-filmhaving a large grain size or a high quality single crystallinesemiconductor thin-film, thereby forming a laminate.

[0100] (2) In order to prevent oxidation and nitridation, flash lampannealing is performed in a hydrogen or a hydrogen-based gas atmosphereunder a reduced-pressure or in a vacuum. As the atmosphere, hydrogen ora mixture of hydrogen and an inert gas (argon, helium, krypton, xenon,neon, or radon) is used, and the gas pressure is in the range of 1.33 Pato less than atmospheric pressure and is preferably in the range of 133Pa to 4×10⁴ Pa. The degree of vacuum is in the range of 1.33 Pa to lessthan atmospheric pressure and is preferably in the range of 13.3 Pa to1.33×10⁴ Pa. However, when an insulating protection film (a siliconoxide film, a silicon nitride film, a silicon oxinitride film, alaminated film composed of silicon oxide and silicon nitride, alaminated film composed of silicon oxide, silicon nitride, and siliconoxide, or the like) is provided on the surface of a low-crystallizationsemiconductor thin-film, or when continuous operation is not performed,flash lamp annealing may be performed in an air or a nitrogen atmosphereat atmospheric pressure.

[0101] When flash lamp annealing is performed in a hydrogen or ahydrogen-containing gas atmosphere under a reduced pressure, gasmolecules, which form the atmospheric gas and which have a high specificheat and a significant thermal cooling effect, collide with thethin-film surface and take the heat from the thin-film when beingremoved. Accordingly, areas where the temperature is low are locallyformed, crystal nuclei are generated in these areas, and crystal growthmay be facilitated in some cases. In the case described above, when anatmospheric gas is a hydrogen gas or a mixture of hydrogen and an inertgas (He, Ne, Ar, or the like), the gasp pressure is set in the range of1.33 Pa to less than atmospheric pressure and is preferably set in therange of 133 Pa to 4×10⁴ Pa. The reason for this is that the effect andadvantages mentioned above can be reliably obtained by the movement ofhydrogen molecules or the like having a high specific heat.

[0102] In addition, when flash lamp annealing is performed, thesubstrate is preferably heated to a strain point thereof or less byusing a resistor heater, an infrared lamp, or the like. A heat resistantresin substrate composed of polyimide or the like or a glass substratehaving a low strain point, such as borosilicate glass or aluminasilicate glass, is heated to 200 to 500° C. and is preferably heated to300 to 400° C., and a heat resistant substrate such as quartz glass orcrystallized glass is heated to 200 to 800° C. and is preferably heatedto 300 to 600° C.

[0103] As methods for performing flash lamp annealing, there are: (1) asimultaneous flash emission in which the entire large area issimultaneously irradiated at least once with flash emission light; (2) ascanning emission in which the same area is scanned at least once withflash emission light; and (3) a step and/or repeat emission in which,while the substrate is relatively moved in a step mode and/or in arepeat mode with respect to flash emission light, flash emission isperformed at least once. In particular, the operations are describedbelow. When necessary, scanning may be performed in an overlappingmanner so that the same area may be irradiated with flash emission lightonce or repeatedly as required.

[0104] (1) Simultaneous Flash Emission

[0105] For example, a substrate having a large area of 1,000 mm by 1,000mm is simultaneously irradiated with flash emission light once orrepeatedly as required.

[0106] (2) Flash Emission by Galvanometer Scanning

[0107] A substrate is fixed, and flash emission light, which iscondensed and is homogenized to have a square shape of, for example, 200mm by 200 mm, is scanned in the same region once or repeatedly asrequired.

[0108] (3) Flash Emission in a Step & Repeat Mode

[0109] The position of flash emission light, which is condensed andhomogenized to have a square shape of, for example, 200 mm by 200 mm, isfixed, and the substrate is moved precisely in the X and the Ydirections so that the same region is irradiated with flash emissionlight once or repeatedly as required.

[0110] Flash lamps can repeatedly emit light in a flashing manner. Forexample, xenon lamps, xenon-mercury lamps, xenon-krypton lamps, kryptonlamps, krypton-mercury lamps, xenon-krypton-mercury lamps, and metalhalide lamps may be preferably used.

[0111] Emission light from a flash lamp is preferably controlled atleast to have an emission spectrum in the ultraviolet wavelength region(when necessary, increase in substrate temperature may be prevented byusing an IR-blocking filter or an IR-reducing filter, which blocks orreduces at least infrared rays, such as a color filter glass(IR-absorbing filter) containing an IR-absorbing material such aspowdered copper, powdered iron, or phosphoric acid; a cold mirror/coldfilter which is coated with an IR-reflecting film such as an ITO film;or a filter (such as an IR-absorbing filter coated with an IR-reflectingfilm) formed of the films described above laminated to each other). Inaddition, a light-emitting apparatus containing a light source lampwhich emits ultraviolet rays or the like and a flash discharge mechanismmay be used, the flash discharge mechanism being able to optionallycontrol a peak discharge current supplied to the flash lamp in flashlamp annealing, the time span thereof, and a repeating speed of lampemission.

[0112] For example, when a lamp having the same shape as the xenon flashlamp having an emission spectrum shown in FIG. 8, and when a capacitoris discharged after being charged at a higher voltage, the peak value ofa discharge current waveform in discharge is increased, and as a result,spectral intensity in the ultraviolet region having a wavelength of 400nm or less is relatively increased. In addition, when the voltage forcharging the capacitor is constant, ⅓ pulse width is decreased and thepeak value of a discharge current waveform is increased with decrease ininductance, and as a result, spectral intensity in the ultravioletregion having a wavelength of 400 nm or less is relatively increased.

[0113] In order to facilitate the polycrystallization so as to form alarge grain size (high carrier mobility) and single crystallization bythe graphoepitaxial and heteroepitaxial growth described above, sincesilicon once fused is preferably cooled slowly, a flashing time (pulsewidth) and the peak value in flash lamp annealing, and the repeatingspeed and frequency for lamp emission are optionally controlled. Inparticular, since longer ⅓ pulse width gives a better result, it is setto, for example, 1 millisecond or more and is preferably 1.5milliseconds or more. In addition, it is preferable that the ⅓ pulsewidth be optionally changed in accordance with a method formanufacturing a low-crystallization semiconductor thin-film, thethickness thereof, the irradiation area, the shape thereof, and thelike.

[0114] A flash lamp source apparatus of the present invention may haveat least one of the structures (1) to (4) described below.

[0115] (1) A reflecting member is provided in a housing, which containsa lamp therein, and is at the earth potential, and when necessary,minute irregularities are formed on the surface of the reflecting membermentioned above. In particular, in a metal housing which is at the earthpotential and which is cooled by a circulating coolant (pure water orthe like), the reflecting member (aluminum plate or the like) isprovided, and minute irregularities (blast treatment, etching, or thelike) may be formed on the surface of the reflecting member so as toobtain uniform illumination of reflected light by diffused reflection.

[0116] (2) A lamp and a reflecting member are provided in a housinghaving shading properties, and when necessary, flash emission light maybe allowed to pass through a transparent member having IR-absorbingproperties or IR-blocking properties. In particular, the flash lamp, thereflecting member, and the like are provided in a metal housing havingthe shading properties, and when necessary, the light is efficientlyemitted in a predetermined direction via an IR-blocking filter or anIR-reducing filter, which blocks or reduces at least infrared rays, suchas a color filter glass (IR-absorbing filter) containing an IR-absorbingmaterial such as powdered copper, powdered iron, or phosphoric acid; acold mirror/cold filter which is coated with an IR-reflecting film suchas an ITO film; or a filter (for example, a filter formed of anIR-absorbing filter coated with an IR-reflecting film) formed of thefilms described above laminated to each other.

[0117] (3) A lamp and a reflecting member are provided in a housing, andflash emission light reflected and condensed and flash emission lightpassing in the forward direction are transmitted through a condensinglens or a light homogenizer. In particular, in the case in whichirradiation is performed by flash light in a band form, a concavecondensing and reflecting member, which is cooled by a circulatingcoolant (pure water or the like), is placed at the rear side of aplurality of flash lamps, flash emission light reflected and condensedand flash emission light passing in the forward direction are furthercondensed by a condensing lens located at the front side, therebyforming flash emission light in a band form having improvedillumination. In addition, in the case in which the entire large area issimultaneously irradiated with flash emission light in a square form orin a rectangular form, a reflecting member, which is cooled by acirculating coolant (pure water or the like), is placed at the rear sideof a plurality of flash lamps, flash emission light reflected and flashemission passing forward are processed by a light uniformer (lighthomogenizer or the like), thereby improving the uniformity inillumination. In the case described above, when necessary, the light maytransmitted through the IR-reducing filter or the IR-blocking filter. Inaddition, this light uniformer (light homogenizer or the like) may becoated with an IR-reflecting film.

[0118] (4) A reflecting member and a housing are cooled by a circulatingcoolant such as pure water.

[0119] In addition, a trigger electrode is preferably provided on theexternal wall of a lamp used for flash lamp annealing (trigger method).In the case described above, it is preferable that a flash lamp beformed as a parallel plate light-emitting tube, that a pair or pluralpairs of counter electrodes be disposed in this light-emitting tube, anda thin-film pattern for forming the trigger electrode or a triggerelectrode assembly be formed for at least one pair of the counterelectrodes on the external wall of the light-emitting bulb tube.

[0120] In addition, plural pairs of counter electrodes are provided in astraight light-emitting tube, and the trigger electrode assemblies orthe thin-film patterns for forming the trigger electrodes may beprovided on the external wall of this light-emitting tube between thesecounter electrodes.

[0121] A method for turning on a flash lamp is different from that for ageneral incandescent lamp, and since a gas such as xenon enclosed in thelamp is electrically insulating material, an electrical path (streamer)in which a current flows is formed beforehand on the inside wall of thelamp by breaking the insulation using a trigger voltage generated by aspecific high-voltage generating circuit. Charges charged and storedbeforehand in a main discharging capacitor by a DC current aredischarged along this path, and hence, the lamp is turned on. There aretwo lamp turning-on modes, one mode is a method (simmer method) inwhich, when a lamp is repeatedly turned on, a small standby current isalways supplied for maintaining an electrical path in order to easilyperform turning-on so that main discharge can be easily performed, andthe other mode is a method (trigger method) in which without using astandby current, a high voltage is applied at each turning-on operationto break the insulation of a gas enclosed so that the lamp is turned on.In each method described above, a flash discharge mechanism (a DC powersupply, a capacitor for storing charges, a coil for controlling acurrent waveform in discharging, a flash lamp, and the like), which canflash light once or repeatedly, is provided.

[0122] Both methods may be applied to the present invention. Concerningthe trigger method, in a conventional flash lamp structure, twoelectrodes is disposed in the vicinities of both ends of a straightlight-emitting tube made of, for example, quartz glass 10 mm in diameterand 150 mm in length so as to oppose each other, and a trigger electrodeassembly is provided on the external wall of the light-emitting tube;however, according to the present invention, in addition to thestructure described above, the structure may also be used in which apair or plural pairs of electrodes are provided in the vicinities ofboth ends of, for example, a parallel plate light-emitting tube 150 mmlong, 100 mm wide, and 10 mm high so as to oppose each other and inwhich thin-film patterns for trigger electrodes or trigger electrodeassemblies are provided on the external wall of the light-emitting tube.In the case described above, by processing (blast, etching, or the like)the wall surface (inside, outside, or both sides) of the light-emittingtube formed of quartz glass to form minute irregularities, theuniformity in illumination of the flash emission light may be improved.In addition, in the case of a parallel plate light-emitting tube, eachdistance between a plurality of cathodes, each distance between aplurality of the anodes, and each distance between trigger metal wiresor the patterns for the trigger electrodes are preferably equivalent toeach other.

[0123] In the parallel plate (rectangular parallelepiped) light-emittingtube, since the structure is formed in which a pair or plural pairs ofelectrodes are provided in the vicinities of both ends of, for example,a parallel plate light-emitting tube 150 mm long, 100 mm wide, and 10 mmhigh so as to oppose each other and in which thin-film patterns fortrigger electrodes or trigger electrode assemblies are provided on theexternal wall of the light-emitting tube, the flash emission area can beincreased, and the uniformity of illumination of the emission light canbe performed. In addition, in the case in which a parallel platelight-emitting tube and a straight light-emitting tube are formed ofquartz glass, by processing (blast, etching, or the like) the wallsurface (inside, outside, or both sides) of the light-emitting tube toform minute irregularities thereon, the uniformity in illumination ofthe flash emission light may be obtained. In addition, as the lampshape, a U shape, a spiral shape (a mosquito coil shape), a spiral andconcentric shape may be used.

[0124] When minute irregularities are formed, as described above, on theexternal wall of a bulb or a rectangular parallelepiped of a flash lamp(see Utility Model No. 2555672) which is formed by steps of providing atransparent conductive film on the external bulb wall, providing aspiral metal wire having spring properties on the film mentioned above,one end of the metal wire being freed, and fixing the other end thereofon the film with a conductive paint, the uniformity in illumination offlash emission light and the adhesion of the transparent conductive filmare improved, the adhesion of the spiral metal wire having the springproperties is also improved, and hence, stable light emission and alonger life can be achieved.

[0125] For example, although a parallel plate light-emitting tube 150 mmlong, 100 mm wide, and 10 mm high has a light emission area ten timesthat of a straight light-emitting tube 150 mm long and 10 mm indiameter, since the flash emission can be performed at a low powerconsumption as a whole, the efficiency is high, the cost is low, theexchange frequency is low, and hence, cost reduction can be realized.

[0126] In the case described above, when a transparent conductive filmor a metal film is patterned to form trigger electrode wires in parallelat the opposite surface side of the parallel plate light-emitting tubefrom the light exist side, variation in discharge among the pluralitypairs of electrodes can be decreased, and as a result, stable lightemission and a longer life can be achieved.

[0127] When a reflecting member which is being cooled is provided at therear side of the light-emitting tube, the temperature does not becomehigh during operation, functions of the reflecting member are notdegraded, the lamp performance is stabilized, and the conditions insidethe housing are not degraded since undesired gases are not generated,whereby stable light emission and a longer life can be achieved.

[0128] In addition, when a plurality of lamps is used for the flash lampannealing described above and is disposed in parallel in plan view, atleast two lamps are connected to each other in series and are connectedto a corresponding power supply, each lamp is connected to acorresponding power supply, or all the lamps are connected in series andare connected to a common power supply, whereby the plurality of thelamps may simultaneously emit light when being synchronously triggered.

[0129] In addition, it is preferable that flash lamps be contained in avacuum container and that a reflecting member be fixed in the vacuumcontainer with a vibration-absorbing material provided therebetween.

[0130] In addition, after an insulating protection film, such as asilicon oxide film, a silicon nitride film, a silicon oxinitride film, alaminated film composed of silicon oxide and silicon nitride, or alaminated film composed of silicon oxide, silicon nitride, and siliconoxide, having an appropriate thickness is formed on the surface of thelow-crystallization semiconductor thin-film described above, the flashlamp annealing described above is preferably performed in the statedescribed above. For example, when the flash lamp annealing is performedby flash emission for the low-crystallization semiconductor thin-film orthe low-crystallization semiconductor thin-film provided with theinsulating protection film, the flash emission is preferably performedon the top surface or the bottom surface, or is simultaneously performedon the top and the bottom surfaces (however, when the irradiation isperformed at the side except the top surface side, the substrate istransparent (which allows light having a wavelength of 400 nm or less topass therethrough).

[0131] In the case described above, it is preferable that islands eachhaving a desired area and a desired shape be formed on thelow-crystallization semiconductor thin-film or the low-crystallizationsemiconductor thin-film covered with the protecting insulation film andthat the flash emission be performed in a nitrogen at atmosphericpressure or in an air or be performed in a hydrogen or ahydrogen-containing gas atmosphere under a reduced pressure or in avacuum (these conditions may also be used for those of other flashemission).

[0132] In order to suppress increase in substrate temperature, todecrease film stress, to prevent the occurrence of cracking in the filmdue to instantaneous expansion of a gas contained (hydrogen or the like)therein, and to form large grain size by slow cooling, it is morepreferable that islands having a desired area and a desired-shape beformed by patterning on the low-crystallization semiconductor thin-filmcovered with the protecting insulation film, and that the flash lampannealing be performed in the state described above.

[0133] In addition, the flash lamp annealing is preferably performedunder the influence of a magnetic field and/or an electric field.

[0134] In flash lamp annealing, when the substrate is heated to a strainpoint thereof or less or is preferably heated to a temperature in therange of 300 to 500° C., dehydrogenation of the low-crystallizationsemiconductor thin-film in annealing, improvement in crystallineuniformity, decrease in stress of the film and the substrate,improvement in emission energy efficiency, increase in throughput, andthe like can be realized. In this connection, before flash lampannealing is performed, heat treatment (for example, at 420 to 450° C.for 30 minutes) for dehydrogenation of the low-crystallizationsemiconductor thin-film may be performed.

[0135] From the polycrystalline or the single crystalline semiconductorthin-film obtained by the flash lamp annealing, channel, source, anddrain regions of MOSTFTs, diodes, wires, resistors, capacitors,electron-emitting elements or the like may be formed. In this case,after the formation of the channel, source, and drain regions, diodes,resistors, capacitors, wires, electron-emitting elements, and the like,when this flash lamp annealing is performed for the regions thereof,recrystallization and activation of n-type and p-type dopants in thefilms can be performed. In addition, when flash lamp annealing isperformed after the regions described above are patterned (formation ofislands) so as to have a desired area and a desired shape, substratedamage (cracking, breaking, or the like) caused by an increase intemperature can be prevented, and in addition, chipping in the filmcaused by a rapid increase in temperature can also be prevented.

[0136] The present invention is suitably used for forming thin-films foruse in silicon semiconductor devices, silicon semiconductor integratedcircuit devices, silicon-germanium semiconductor devices,silicon-germanium semiconductor integrated circuit devices, III-V andII-VI compound semiconductor devices, III-V and II-VI compoundsemiconductor integrated circuit devices, silicon carbide semiconductordevices, silicon carbide semiconductor integrated circuit devices,polycrystalline or single crystalline diamond semiconductor devices,polycrystalline or single crystalline diamond semiconductor integratedcircuit devices, liquid crystal display devices, organic or inorganicelectroluminescent (EL) devices, field emission display (FED) devices,light-emitting polymer display devices, light-emitting diode displaydevices, CCD area/linear sensor devices, CMOS or MOS sensor devices,solar cells, and the like.

[0137] For example, from this thin-film, a top gate type, a bottom gatetype, a dual gate type, or a back gate type MOSTFT are formed, andelectrooptic display devices, such as liquid crystal display devices,organic EL display devices, and FED display devices, including aperipheral driving circuit, an image signal processing circuit, a memorycircuit, and the like, which are formed of the MOSTFTs described above,can be obtained.

[0138] In the case described above, when semiconductor devices,electrooptic display devices, solid-phase imaging devices, or the likehaving an internal circuit and a peripheral circuit are manufactured,channel, source, and drain regions of MOSTFTs forming at least one ofthese circuits may be formed by using the polycrystalline or singlecrystalline semiconductor thin-film, and the peripheral driving circuit,image signal processing circuit, memory circuit, and the like may beintegrated with each other.

[0139] In addition, an EL element structure may be formed in which acathode or an anode connected to the drain or the source of the MOSTFTis provided under each of organic or inorganic electroluminescent layers(EL layers) for individual colors.

[0140] In this case, when the cathode covers active elements such as theMOSTFT and diode, in the structure in which the anodes are provided atthe upper side, in addition to increase in light emission area, thegeneration of leakage current caused by emission light incident on theactive element can be prevented due to the shading effect of thecathode. In addition, when the cathode or the anode is provided on theentire surfaces of the individual organic or inorganic EL layers forindividual colors and therebetween, since the entire surface is coveredwith the cathode or the anode, the degradation of the organic EL layershaving inferior moisture resistance and the oxidation of the electrodesare prevented, and hence, longer life, higher quality, and higherreliability can be obtained. In addition, since heat dissipating effectis improved when the entire surface is covered with the cathode, thechange in structure (fusion or recrystallization) of an organic ELthin-film caused by heat generation is decreased, longer life, higherquality, and higher reliability can be obtained. Accordingly, full colororganic EL layers having high accuracy and high quality can be formedwith high productivity, and hence, cost reduction can be achieved.

[0141] In addition, when a black mask layer composed of chromium,chromium dioxide, or the like is formed between the organic or inorganicEL layers for individual colors, light leakage between colors or betweenpixels is prevented, and the contrast can be improved.

[0142] When the present invention is applied to a field emission display(FED) device, it is preferable that the emitter (electric field emissioncathode) be connected to the drain of the MOSTFT via the polycrystallineor single crystalline semiconductor thin-film and, in addition, beformed of an n-type polycrystalline semiconductor film grown on thepolycrystalline or single crystalline semiconductor thin-film describedabove, a polycrystalline diamond film, a carbon thin-film which may ormay not contain nitrogen, or a number of minute protruding structures(for example, carbon nanotube) formed on a surface of a carbon thin-filmwhich may or may not contain nitrogen.

[0143] In this case, when a metal shielding film (when this film isformed of the same material and in the same step as those for forming agate lead electrode of the FED, it is advantageous since the process canbe simplified) at the earth potential is formed above the activeelements, such as the MOSTFT or a diode, with an insulating filmtherebetween, the formation of undesired inversion layer in an activeelement located under the insulating layer, this formation being causedby positive charges, accumulated on the insulating layer, of gases in anairtight container which are positively ionized by electrons emittedfrom the emitter can be prevented, and abrupt increase of emittercurrent caused by an excess current flow via this inversion layer canalso be prevented. In addition, the generation of leakage current causedby electrons and holes generated in the gate channel of the MOSTFT, theelectrons and holes being generated by light emitted from a fluorescentbody by collision with electrons emitted from the emitter, can also beprevented.

[0144] The present invention also provides a method for forming asemiconductor thin-film and a method for manufacturing a semiconductordevice, and the method mentioned above comprises a first step of forminga low-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; asecond step of performing pre-baking in which the substrate is heated toa strain point thereof or less; a third step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state to facilitate the crystallization thereof by flashlamp annealing in assist-baking in which the substrate is heated to thestrain point thereof or less; and a fourth step of performingpost-baking in which the crystallized semiconductor thin-film is heateduntil the temperature thereof is decreased at least to the stain pointof the substrate or less.

[0145] In the method described above, the low-crystallizationsemiconductor thin-film and the flash lamp annealing described above areas defined previously, and the individual heat treatment described aboveare important by the following reasons (these definition and theimportance are also applied to those in the methods described below).

[0146] <Pre-Baking>

[0147] When flash lamp annealing is performed while gases (oxygen,nitrogen, carbon dioxide gas, and the like) or moisture adhere to thelow-crystallization semiconductor thin-film, and gases (hydrogen gas orthe like generated in film formation by plasma CVD) formed in filmformation are contained therein, stress defects caused by abruptincrease in film and substrate temperature, such as film peeling andfilm cracking by expansion and explosion of hydrogen gas, and substratedamage (glass crystallization and the like) occur. In order to preventthe defects described above, the factors causing the defects are removedby pre-baking.

[0148] The pre-baking is performed at a temperature in the range of fromroom temperature to the strain point of the substrate, for example, 300to 500° C., by heating means such as resistor heater, halogen lamp, orthe like. A baking time is preferably optimized in consideration of afilm thickness and film quality of the low-crystallization semiconductorthin-film determined by film-forming conditions (vapor-phase growth,sputtering, deposition, or the like); a material and size of thesubstrate; and the like, and the baking time is preferably set to, forexample, 5 to 20 minutes.

[0149] In addition, heat treatment may be performed beforehand in adifferent heating apparatus at a dehydrogenation temperature(approximately 420° C.) for amorphous silicon thin-films formed byplasma CVD; however, by the reason described above, it is naturallyunderstood that the pre-baking in the flash lamp annealing apparatusmust be performed.

[0150] <Assist-Baking>

[0151] When the low-crystallization semiconductor thin-film is fused byan abrupt increase in film temperature by flash emission for an ultrashort time, such as 1.5 milliseconds, stress damages, such as filmpeeling, film cracking, substrate cracking, or substrate chipping, arelikely to occur due to temperature difference between the substrate andthe fused silicon. Accordingly, in order to decrease the stress damageby decreasing the temperature difference, the substrate is preferablymaintained at a predetermined temperature during flash emission.

[0152] In the assist-baking, the temperature is maintained in the rangeof from room temperature to the strain temperature of the substrate, forexample, 300 to 500° C., and the flash lamp annealing conditions areoptimized in consideration of a film thickness and film quality of thelow-crystallization semiconductor thin-film determined by film-formingconditions (vapor-phase growth, sputtering, deposition, or the like); amaterial and size of the substrate; and the like.

[0153] <Post-Baking>

[0154] Flash lamp annealing for an ultra short time such as 1.5milliseconds in assist-baking, which heats and cools thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state, facilitates the crystallization thereof, and inaddition, when slow cooling is performed, improvement in crystallinityand TFT properties can be expected by formation of a larger crystalgrain size, decrease in film stress, and the like.

[0155] In contrast, when quenching is performed, stress damages, such asfilm peeling, film cracking, substrate cracking, or substrate chipping,are likely to occur due to temperature difference between the substrateand the fused silicon. Accordingly, in order to decrease the thermalstress by decreasing this large temperature difference, after flash lampannealing, the substrate and the crystallized semiconductor thin-filmare preferably maintained at least for a certain period of time, such as1 to 10 minutes, until the temperature thereof is decreased to thepre-baking or assist-baking temperature.

[0156] Accordingly, sequential operation may be performed, that is, oneheating apparatus capable of performing various baking purposes isprepared; the pre-baking temperature, the assist-baking temperature, andpost-baking temperature are set to the same temperature as thedehydrogenating temperature (approximately 420° C.) of amorphous siliconthin-film formed by plasma CVD; flash lamp annealing is performed afterpre-baking is performed for the predetermined time; and the substrate istaken out after being maintained for a predetermined time, such as 1 to10 minutes.

[0157] As the substrate, there may be mentioned low strain point glasssubstrates (borosilicate glass, aluminosilicate glass, reinforced glass,or the like), high strain point glass substrates (synthetic quartzglass, fused quartz glass, crystallized glass, or the like), heatresistant resin substrates (polyimide or the like), ceramic substrates,metal or ceramic substrates coated with an insulating film, silicon orcompound semiconductor substrates coated with an insulating film, andthe like. These mentioned above may be selectively used, as required.

[0158] In the method described above, it is preferable that the firststep, the second step, the third step, and the fourth step be repeatedlyperformed.

[0159] In addition, the emission time (⅓ pulse width) of flash lampannealing suitably for the pre-baking, assist-baking, and post-baking ofthe substrate is 0.1 microseconds or more and is preferably 0.5 to 3milliseconds.

[0160] That is, in flash lamp annealing for crystallization, flashemission conditions are preferably determined in consideration of heatresistance of the substrate, desired electron/hole mobility (includingcrystal grain size), and the like. In the case of heat resistant glass,such as quartz glass or crystallized glass, when the emission time isset as long as possible, for example 1.5 to 3 milliseconds, the crystalgrains become larger since fused silicon is slowly cooled, and forexample, crystallized silicon thin-film having high electron/holemobility can be obtained.

[0161] In contrast, in the case of low strain point glass, such asborosilicate glass, aluminosilicate glass, or reinforced glass, or aheat resistant resin such as polyimide, the emission time must be set,for example 0.5 to 1.5 milliseconds, in consideration of a balancebetween prevention of substrate damage and desired electron/holemobility (including crystal grain size). In addition, in flash lampannealing for ion activation, since heating time for silicon innon-fusion state (for example, at 700 to 1,000° C.) is preferable, theemission time (for example, 3 milliseconds or more) is preferably set aslong as possible.

[0162] Furthermore, the present invention provides methods (a) to (r) ordevices described below.

[0163] (a) A method for manufacturing an electrooptic device, whichcomprises a step of patterning a low-crystallization semiconductorthin-film which may or may not contain at least one Group IV elementsuch as tin so that irradiation areas and shapes thereof in active andpassive element regions in a pixel display portion and in active andpassive element regions in a peripheral circuit portion are equivalentto each other; a step of subsequently performing appropriate flash lampannealing of the substrate in pre-baking, assist-baking, andpost-baking; and a step of, when necessary, patterning each crystallizedregion to have a predetermined area and predetermined dimensions.

[0164] In the method described above, the crystallization level of thelow-crystallization semiconductor thin-film by flash lamp annealing isproportional to the thickness and the irradiation area thereof. That is,since the absorption of flash emission light energy is increased withincreasing thickness and irradiation area, crystallization isfacilitated.

[0165] Accordingly, in order to uniform the crystallization level indisplay devices such as an LCD, an organic El (electroluminescence), orthe like, it is necessary that, in addition to the thicknesses, theirradiation areas and the sizes of the low-crystallization-semiconductorthin-films, which correspond to the pixel display portion and peripheralcircuit portion, be equivalent to each other by common lithographic andetching techniques. For example, TFT regions in the pixel displayportion and the peripheral circuit portion are formed to be equivalentto each other, and in addition, areas of diodes, resistors, and the likein the peripheral circuit are formed to be equivalent to each other. Inaddition, after this flash lamp annealing, each crystallized region ispreferably patterned so as to ensure areas and shapes on which optionalTFTs, diodes and resistors are formed.

[0166] (b) A method for manufacturing an electrooptic devices, whichcomprises a step of patterning a low-crystallization semiconductorthin-film, which may or may not contain at least one Group IV elementsuch as tin, so that irradiation areas and shapes thereof in active andpassive element regions in a peripheral circuit portion is larger thanthose in active and passive element regions in a pixel display portion;a step of subsequently performing appropriate flash lamp annealing ofthe substrate in pre-baking, assist-baking, and post-baking; and a stepof, when necessary, patterning each crystallized region to have apredetermined area and predetermined dimensions.

[0167] In the case of LCD panels of projectors, as the measure againstleakage current of a pixel display TFT caused by light leakage ofintensive incident light, it may be preferable in some cases when avoltage driving TFT in the pixel display portion is formed of anamorphous or a microcrystalline silicon film having low mobility andwhen a current driving TFT in the peripheral circuit portion is formedof a polycrystalline or a single crystalline silicon film having highmobility.

[0168] Accordingly, by performing flash lamp annealing after theirradiation areas and the sizes of the individual TFT, diode, andresistor regions in the peripheral circuit portion are patterned largerthan that of the TFT regions in the pixel display region by commonlithographic and etching techniques, the low-crystallizationsemiconductor thin-films in the individual TFT, diode, and resistorregions in the peripheral circuit portion are preferably converted intothe polycrystalline or the single crystalline silicon films having highmobility, and the low-crystallization semiconductor thin-film in thepixel display region is preferably converted into an amorphous or amicrocrystalline silicon film having low mobility. In addition, afterthis flash lamp annealing, the individual regions thus crystallized arepreferably patterned so as to have areas and shapes of predeterminedTFTs, diodes, and resistors.

[0169] (c) A method for manufacturing a semiconductor substrate or asemiconductor device, which comprises a step of forming a recess portionin a predetermined element-forming region of a substrate, the recessportion being provided with a step having a predetermined shape andpredetermined dimensions, or after a laminate of an oxide-basedinsulating film-1, a nitride-based insulating film-1, and an oxide-basedinsulating film-2 or a laminate (for example, SiO₂-1/SiN-1/SiO₂-2) ofthe oxide-based insulating film-1, the nitride-based insulating film-1,the oxide-based insulating film-2, and a nitride-based insulating film-2is formed on the substrate, a step of forming a recess portion in apredetermined element-forming region of the former oxide-basedinsulating film-2 or the latter nitride-based insulating film-2, therecess portion being provided with a step having a predetermined shapeand predetermined dimensions; a step of forming a low-crystallizationsemiconductor thin-film which may or may not contain at least one GroupIV element such as tin and, when necessary, a reflection-reducing,protective, insulating film on the substrate including the recessportion; a step of forming a single crystalline semiconductor thin-filmat least in the recess portion in accordance with graphoepitaxial growthusing a bottom corner of the step as a seed by appropriate flash lampannealing of the substrate in pre-baking, assist-baking, andpost-baking; a step of processing the surface of this single crystallinesemiconductor thin-film by CMP (Chemical Mechanical Polishing) or byselective etching so as to form a single crystalline semiconductorthin-film having a predetermined thickness and area, the singlecrystalline semiconductor thin-film having islands formed thereon; and astep of, when necessary, forming an SCSOS (Single Crystal Semiconductor(Silicon) On Substrate, for example, SCSOG (Single Crystal Semiconductor(Silicon) On Glass)) substrate provided with a gate insulating film oran insulating protection film by high temperature thermal oxidation, lowtemperature and high pressure annealing (including subcritical waterreaction or supercritical water reaction described later: hereafter, thesame as above), CVD, or the like.

[0170] (d) A method for manufacturing a semiconductor substrate or asemiconductor device, which comprises a step of forming, when necessary,a laminate (for example, SiO₂-1/SiN-2/SiO₂-2) of the oxide-basedinsulating film-1, the nitride-based insulating film-1, and theoxide-based insulating film-2 on a substrate; a step of forming amaterial layer (for example, a crystalline sapphire thin-film) havinggood lattice matching properties with a single crystalline semiconductoron the laminate; a step of forming a low-crystallization semiconductorthin-film which may or may not contain at least one Group IV elementsuch as tin and, when necessary, a reflection-reducing, protective,insulating film on this material layer; a step of forming a singlecrystalline semiconductor thin-film in accordance with heteroepitaxialgrowth using this material layer as a seed by appropriate flash lampannealing of the substrate in pre-baking, assist-baking, andpost-baking; a step of processing the surface of this single crystallinesemiconductor thin-film by CMP or by selective etching so as to form asingle crystalline semiconductor thin-film having a predeterminedthickness; and a step of, when necessary, forming an SCSOS substrate,such as an SCSOG substrate, provided with a gate insulating film or aninsulating protection film formed by high temperature thermal oxidation,low temperature and high pressure annealing, CVD, or the like.

[0171] In these (c) and (d) methods, by performing CMP or selectiveetching of the reflection reducing, protective insulating film and thesurface of the single crystalline semiconductor thin-film thus formed,an SCSOS such as an SCSOG substrate provided with a single crystallinesilicon film having a desired thickness and area. In addition, in bothmethods (c) and (d), after this CMP or selective etching, when a gateinsulating film or a protection film is formed by high temperatureoxidation, low temperature and high pressure annealing, CVD, or thelike, MOSLSIs (Large Scale Integration), BiCMOS LSIs, Bipolar LSIs, andthe like can be manufactured.

[0172] In the step described above, in order to prevent contamination byimpurities from the substrate, a nitride-based insulating film (siliconnitride film, silicon oxinitride film, or the like) having anappropriate thickness must be formed over the entire surface of thesubstrate in some cases; however, in this case, in order to improve theadhesion between the substrate and the nitride-based insulating film, anoxide-based insulating film (silicon oxide film or the like) having anappropriate thickness must be provided between the substrate and thenitride-based insulating film.

[0173] Furthermore, as the substrate, there may be mentioned low strainpoint glass substrates (borosilicate glass, aluminosilicate glass,reinforced glass, or the like); high strain point glass substrates(synthetic quartz glass, fused quartz glass, crystallized glass, or thelike); heat resistant resin substrates (polyimide or the like); metalsubstrates (iron, copper, aluminum, alloys such as stainless steel, orthe like); ceramic substrates; metal substrates, low strain point glasssubstrates, heat resistant resin substrates, or ceramic substratescoated with a high melting point metal (titanium, tantalum, molybdenum,tungsten, alloys thereof, such as a molybdenum-tantalum alloy, or thelike) or/and a metal silicide (WSi₂, MoSi₂, TiSi₂, TaSi₂, CoSi, Pd₂Si,Pt₂Si, CrSi₂, NiSi, RhSi or the like); silicon substrates; compoundsemiconductor substrates; or the like.

[0174] (e) A method for manufacturing a single crystalline semiconductorthin-film or a single crystalline semiconductor device, which comprisesa step of forming an n-type or/and a p-type doped region (such assource/drain or source/gate channel/drain) in the single crystallinesemiconductor thin-film of the SCSOS substrate, such as an SCSOGsubstrate, formed according to the above (c) or (d) by ion implantationor ion doping; and a step of activating doped ions by appropriate flashlamp annealing of the substrate in pre-baking, assist-baking, andpost-baking by using at least an IR-reducing or an IR-blocking film.

[0175] (f) A method for manufacturing a single crystalline semiconductorthin-film or a single crystalline semiconductor device, which comprisesa step of forming an n-type or/and p-type doped regions (such assource/drain or source/gate channel/drain) in a single crystallinesemiconductor thin-film of a crystalline semiconductor (Si, SiGe, SiC,GaAs, or the like) substrate, such as an SOI (Silicon on Insulator)substrate by ion implantation or ion doping; and a step of activatingdopant ions by appropriate flash lamp annealing of the substrate inpre-baking, assist-baking, and post-baking by using at least anIR-reducing or an IR-blocking filter.

[0176] In the near future, in a silicon MOSLSI having a 0.07-μm node,the junction depth at the source and the drain will be decreased to 10to 15 nm. However, according to a current annealing (RTA: Rapid ThermalAnneal) technique using a tungsten-halogen lamp, since the emission timeis long such as in the order of several seconds, n-type or/and p-typedopants are thermally diffused, and it has been difficult to form ashallow junction. Hence, it has been believed that a junction depth ofup to 20 nm is a technical limitation.

[0177] However, in flash lamp annealing of the present invention, sinceion activation can be performed by heating in a non-fusion state usingan xenon lamp for an emission time in the order of several milliseconds,such as 1 to 5 milliseconds, the technical limitation can be overcome,and hence, an ultra-shallow junction depth of 20 nm or less can berealized.

[0178] However, since flash emission light of this xenon lamp has anemission spectrum having an intensive peak at a wavelength of 800 to1,000 nm in the infrared region, a heating temperature of a siliconlayer varies due to a large variation in intensive light absorption inthis region, the degree of ion activation of implanted n-type or/andp-type dopants and the thermal diffusion level thereof are likely tovary, and hence, it has been relatively difficult to form a shallowerjunction depth with good repeatability. Accordingly, as described above,during appropriate flash lamp annealing of the substrate in a non-fusionstate in pre-baking, assist-baking, and post-baking, an intensiveemission peak in a region having a wavelength of 800 to 1,000 nm isreduced or cut by using at least an IR-reducing or an IR-blocking filterso as to perform controlled heating of a silicon layer by irradiationwith ultraviolet rays with or without visible rays, which are in astable flash emission region, ion activation can be performed whilethermal diffusion level of implanted n-type or/and p-type dopants iscontrolled, and hence, a ultra-shallow junction depth can be formed. Inthe steps described above, the conditions of the pre-baking,assist-baking, and post-baking can be optionally determined inconsideration of a substrate material or the like; however, atemperature of 300 to 500° C. is preferable.

[0179] As the method for forming SOI substrates, for example, there maybe mentioned a SIMOX method (a method for forming an SOI substrate byperforming ion implantation of oxygen ions into a single crystallinesilicon substrate followed by annealing at a temperature of 1,300 to1,400° C., which is very close to the melting point), a wafer bondingmethod (a method for forming an SOI substrate by polishing one surfaceof bonded and thermally oxidized-single crystalline silicon substrates),a SMART CUT method (a method for forming an SOI substrate by a step ofperforming ion implantation of hydrogen ions into one thermally oxidizedsingle crystalline silicon substrate followed by bonding with anothersubstrate and thermal oxidation, and a step of removing said anothersubstrate so as to obtain the hydrogen ion implanted single crystallinesilicon layer), or an ELTRAN method (a method for forming an SOIsubstrate by performing epitaxial silicon growth on a porous siliconsubstrate followed by thermal oxidation, a step of bonding the epitaxialsilicon to a supporting substrate followed by thermal oxidation, a stepof separating the epitaxial silicon using a water jet method, and a stepof performing selective etching, annealing in a hydrogen atmosphere, andthe like. It is naturally understood that all the methods describedabove may be used for the present invention.

[0180] (g) A method for manufacturing a polycrystalline or a singlecrystalline semiconductor thin-film, or a polycrystalline or a singlecrystalline semiconductor device, which comprises a step of forming ann-type or/and a p-type doped region (such as source/drain or source/gatechannel/drain) in a polycrystalline or single crystalline semiconductorthin-film on a substrate, which is crystallized by laser{near-ultraviolet (UV) and/or far-ultraviolet (DUV) laser (such as,excimer laser, higher harmonic light wave modulated near-ultraviolet(UV) and/or far-ultraviolet (DUV) laser by nonlinear optical effect),visible ray laser, near-infrared and/or far-infrared laser, or the like}annealing, by ion implantation or ion doping; and a step of activatingdopant ions by appropriate flash lamp annealing of the substrate inpre-baking, assist-baking, and post-baking by using at least anIR-reducing or an IR-blocking filter.

[0181] (h) A method for manufacturing a polycrystalline semiconductorthin-film, or a polycrystalline semiconductor device, which comprises astep of forming an n-type or/and a p-type doped region (such assource/drain or source/gate channel/drain) in a polycrystallinesemiconductor thin-film on a substrate by ion implantation or iondoping, the semiconductor thin-film being crystallized by solid-phasegrowth; and a step of activating doped ions by appropriate flash lampannealing of the substrate in pre-baking, assist-baking, and post-bakingby using at least an infrared-reducing or an infrared-blocking filter.

[0182] (i) A method for manufacturing a polycrystalline or a singlecrystalline semiconductor thin-film, or a polycrystalline or a singlecrystalline semiconductor device, which comprises a step of forming ann-type or/and a p-type doped region (such as source/drain or source/gatechannel/drain) in a polycrystalline or a single crystallinesemiconductor thin-film on a substrate by ion implantation or iondoping, the crystalline semiconductor thin-film being crystallized by acondensing lamp annealing; and a step of activating doped ions byappropriate flash lamp annealing of the substrate in pre-baking,assist-baking, and post-baking by using at least an infrared-reducing oran infrared-blocking filter.

[0183] (j) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a first step of forming alow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; asecond step of forming an n-type or/and a p-type doped region (such assource/drain or source/gate channel/drain) in the low-crystallizationsemiconductor thin-film by ion implantation or ion doping; a third stepof performing pre-baking in which the substrate is heated to a strainpoint thereof or less; a fourth step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,and a non-fusion state by flash lamp annealing in assist-baking, inwhich the substrate is heated to the strain point thereof or less, tofacilitate the crystallization and to active the dopant at the sametime; and a fifth step of performing post-baking in which the substrateis heated until the temperature thereof is decreased to the strain pointthereof or less.

[0184] (k) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a first step of forming alow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; asecond step of performing pre-baking in which the substrate is heated toa strain point thereof or less; a third step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,and a non-fusion state by flash lamp annealing in assist-baking, inwhich the substrate is heated to the strain point thereof or less, tocrystallize the low-crystallization semiconductor thin-film; a fourthstep of performing post-baking in which the substrate is heated untilthe temperature thereof is decreased to the strain point thereof orless; a fifth step of forming an n-type or/and a p-type doped region(such as source/drain or source/gate channel/drain) in the formedpolycrystalline or single crystalline semiconductor thin-film by ionimplantation or ion doping; and a sixth step of heating the substrate ina non-fusion state by appropriate flash lamp annealing in pre-baking,assist-baking, and post-baking to activate the doped ions by using atleast an infrared-reducing or an infrared-blocking filter.

[0185] (l) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a step of forming a shadingunderlying film having highly absorptive properties or highly reflectiveproperties with respect to flash emission light passing through areflection-reducing, protective, insulating film and alow-crystallization semiconductor thin-film, the underlying film havingthermal and electrical conductivities higher than those of thesubstrate; a step of forming, when necessary, an electrical insulatingbuffer film having transmission or shading properties on the underlyingfilm; a step of forming a low-crystallization semiconductor thin-filmwhich may or may not contain at least one Group IV element such as tinon the buffer layer at least in the underlying film region; a step offorming, when necessary, a reflection-reducing, protective, insulatingfilm on the semiconductor thin-film; and a step of heating and coolingthe low-crystallization semiconductor thin-film to a fusion, asemi-fusion, or a non-fusion state by appropriate flash lamp annealingof the substrate in pre-baking, assist-baking, and post-baking tofacilitate the crystallization.

[0186] In the case of a bottom gate TFT, a back gate TFT, a dual gateTFT, or the like, a high thermal conductive and electrical conductivematerial, which is heated by absorbing flash emission light passingthrough the reflection reducing, protective, insulating film and thelow-crystallization semiconductor thin-film, may be used as theunderlying film, and for example, there may be mentioned a coloringmetal (chromium, copper, or the like), a high melting point metal(titanium, tantalum, molybdenum, tungsten, an alloy thereof, such as amolybdenum-tantalum alloy, or the like), or a metal silicide (WSi₂,MoSi₂, TiSi₂, TaSi₂l CoSi, Pd₂Si, Pt₂Si, CrSi₂, NiSi, or RhSi). In thiscase, since the substrate temperature is increased to a relatively highlevel, a high strain point (heat resistant) glass such as quartz glassor crystallized glass, or a ceramic may be suitably used as thesubstrate material.

[0187] In addition, a high thermal conductive and electrical conductivematerial, such as a white color metal {aluminum, an aluminum alloy(1%-silicon-containing aluminum), silver, nickel, platinum, or thelike}, a laminated film of white color metal/a high melting point metal(aluminum/molybdenum or the like), which reflects flash emission lightpassing through the reflection-reducing, protective, insulating film andthe low-crystallization semiconductor thin-film, may be used as theunderlying film. In this case, since the substrate temperature isincreased to a relatively low level, a low strain point glass, such asborosilicate glass, aluminosilicate glass, or reinforced glass, or aheat resistant resin such as polyimide may be suitably used as amaterial for the substrate; however, a high strain point (heatresistant) glass, such as quartz glass or crystallized glass, a ceramic,or the like may also be used.

[0188] In addition, in order to prevent reaction between the underlyingfilm and the low-crystallization semiconductor thin-film caused by flashlamp annealing, the buffer film is formed; however, when the underlyingfilm is formed of a material which does not react with fusedlow-crystallization semiconductor thin-film, the buffer film may beomitted. For example, when the underlying film is formed of aluminumcoated with an insulating film formed by anodizing, a high melting pointmetal (a Mo—Ta alloy or the like), or the like, it is not necessary toform the buffer film.

[0189] As the buffer film, an electrical insulating silicon oxide film,silicon oxinitride film, silicon nitride film, laminated film of siliconoxide and silicon nitride, laminated film of silicon nitride and siliconoxide, laminated film of silicon oxide, silicon nitride, and siliconoxide, or the like may be used.

[0190] When a low strain point glass, such as borosilicate glass oraluminosilicate glass, fused quartz glass, crystallized glass, or a heatresistant resin is used for the substrate, in order to prevent thediffusion of impurities (Na ions or the like) from the substrate, asilicon nitride-based film, such as a silicon oxinitride film, a siliconnitride film, a laminated film of silicon oxide and silicon nitride, alaminated film of silicon nitride and silicon oxide, or a laminated filmof silicon oxide, silicon nitride, and silicon oxide, is preferablyused.

[0191] When being processed by flash emission, since thelow-crystallization semiconductor thin-film on the underlying film isheated by its own properties of absorbing emission light and by theheating and heat-storing effect of the underlying film, fusion of thethin-film is facilitated, and the fused silicon flows out, so that it isdifficult to form a polycrystalline or a single crystalline siliconthin-film on the underlying film. Accordingly, by forming thelow-crystallization semiconductor thin-film only in the underlying filmregion, the fused silicon is prevented from flowing out, and thepolycrystalline or the single crystalline silicon thin-film ispreferably formed only on the underlying film region.

[0192] In addition, when the underlying film is patterned into the shapehaving an area equivalent to or larger than that of thelow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, and having protrudingportions which protrude linearly, thermal dissipation of thelow-crystallization semiconductor thin-film in a fusion, a semi-fusion,or a non-fusion state by flash lamp annealing preferably occurs usingthe protruding portions of the underlying film so as to form nuclei forcrystal growth, and hence, the entire semiconductor thin-film may becrystallized in an optional crystal-orientation.

[0193] In the case described above, since the thermal dissipation ismore effectively performed at the linearly projecting portions than theother parts, and conditions (formation of species or nuclei), which maystart recrystallization, are prepared thereby, the entirelow-crystallization semiconductor thin-film may be converted into apolycrystalline semiconductor thin-film having a large grain size or asingle crystalline semiconductor thin-film, each having an optionalcrystal orientation.

[0194] In addition, after the low-crystallization semiconductorthin-film which may or may not contain at least one Group IV elementsuch as tin is patterned into the shape having an area equivalent to orsmaller than that of the underlying film and having minute projectingportions in the protruding portions of the underlying film, the entirelow-crystallization semiconductor thin-film in a fusion, a semi-fusion,or a non-fusion state by the flash lamp annealing may be crystallized inan optional orientation by using the minute projecting portions asnuclei for crystal growth.

[0195] In this case, as in the case described above, since thermaldissipation is more effectively performed at the minute protrudingportions than the other parts, and conditions (formation of species ornuclei), which may start recrystallization, are prepared thereby, theentire low-crystallization semiconductor thin-film may be converted intoa polycrystalline semiconductor thin-film having a large grain size or asingle crystalline semiconductor thin-film, each having an optionalcrystal orientation.

[0196] In addition, the underlying film is preferably used at anoptional potential (no potential, earth potential, gate potential ofTFT, or the like) via the linear protruding portions.

[0197] In addition, the reflection-reducing, protective, insulating filmis an electrical insulating film that at least allows ultraviolet raysto pass therethrough and may also be used as a gate insulating film.

[0198] As the electrical insulating film which at least allowsultraviolet rays to pass therethrough, for example, there may bementioned silicon oxide film, a silicon nitride film, a siliconoxinitride film, a laminated film of silicon oxide and silicon nitride,a laminated film of silicon nitride and silicon oxide, or a laminatedfilm of silicon oxide, silicon nitride, and silicon oxide, and as thegate insulating film, for example, there may be mentioned silicon oxidefilm, a silicon nitride film, a silicon oxinitride film, a laminatedfilm of silicon oxide and silicon nitride, a laminated film of siliconnitride and silicon oxide, or a laminated film of silicon oxide, siliconnitride, and silicon oxide.

[0199] (m) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a step of, when alow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, is crystallized byheating to a fusion or a semi-fusion state and cooling by flash lampannealing performed in an oxidizing atmosphere, simultaneously formingan oxide-based insulating film (silicon oxide, silicon oxinitride, orthe like) on a surface of this polycrystalline or single crystallinesemiconductor thin-film, wherein this oxide-based film is used as a gateinsulating film or a protection film.

[0200] (o) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a step of forming an oxide-basedinsulating film (silicon oxide film, silicon oxinitride film, or thelike) in a high pressure and low temperature oxidizing atmosphere (air,oxygen, ozone, steam, NO, N₂O, or the like) at a pressure in the rangeof 0.1 to 30 MPa and at a temperature in the range of room temperatureto a strain point of a substrate on a polycrystalline or singlecrystalline semiconductor thin-film, which may or may not contain atleast one Group IV element such as tin, formed on a low strain pointglass, a high strain point glass, or a heat resistant resin substrate byflash lamp annealing, wherein this oxide-based film is used as a gateinsulating film or a protection film.

[0201] In the above method (o), by the reasons (1) to (2) describedbelow, it is preferable that, on the polycrystalline or the singlecrystalline semiconductor thin-film, which may or may not contain atleast one Group IV element such as tin, formed on the low strain pointglass, the high strain point glass, or the heat resistant resinsubstrate by flash lamp annealing, an oxide-based insulating film beformed by a subcritical water reaction or a supercritical waterreaction, which is one type of high pressure and low temperatureannealing, and be used as a gate insulating film or a protection film.

[0202] Subcritical water reaction: reaction with hot water (subcriticalwater) at a temperature and a pressure lower than the critical point(374° C. and 22 MPa) of water

[0203] Supercritical water reaction: reaction with supercritical waterin a state over the critical point (374° C. and 22 MPa) of water

[0204] (1) According to these reactions, a superior gate insulating filmand interface can be formed, crystal defects of the polycrystalline orthe single crystalline thin-film are decreased, the V_(th) and S valueof a TFT are improved, and in addition, yield and reliability of the TFTis improved.

[0205] (2) When a gate insulating film (such as a SiO₂ film) is formedby high temperature oxidation (for example, at 1,050° C. for 60minutes), a warpage of 100 to 150 μm is generated in a quartz wafer 8″in diameter and approximately 800 μm thick for TFT, and this warpage ofthe wafer causes the defects (i) to (v) described below.

[0206] (i) Troubles such as unstable vacuum chucking are likely to occurin photolithographic or etching operation.

[0207] (ii) Variation in focus at the central and peripheral portioncauses variation in accuracy, and problems of decreases in yield andquality may arise frequently.

[0208] (iii) Gap between a TFT substrate and a counter substrate, inwhich liquid crystal is enclosed, is difficult to control when the twosubstrate are bonded with each other, variation in gap of a liquidcrystal layer occurs frequently, and problems of decreases in yield andquality caused by decrease in light transmittance and contrast mayarise.

[0209] (iv) Since flaws are frequently formed on the back surface of aliquid crystal driving (TFT) substrate, optical polishing of the backsurface must be performed, resulting in an increase in cost.

[0210] (v) When the quartz glass size is increased, for example, from 8to 12 inch in diameter, the warpage is further increased, the problemsdescribed above become more serious, and as a result, the yield,quality, and productivity may be easily decreased.

[0211] In contrast, in the above method (o), since the gate insulatingfilm (such as SiO₂ film) is formed by a high pressure and lowtemperature subcritical water reaction or supercritical water reaction,the wafer does not warp and the problems described above are solved, andhence, significant cost reduction can be achieved by improvement inyield, quality, and productivity.

[0212] (p) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a step of forming an oxide-basedinsulating film (silicon oxide film, silicon oxinitride film, or thelike) by performing high temperature thermal oxidation in an oxidizingatmosphere (air, oxygen, ozone, steam, NO, N₂O, or the like) of apolycrystalline or a single crystalline semiconductor thin-film, whichmay or may not contain at least one Group IV element such as tin, formedon a high strain point glass by flash lamp annealing, wherein thisoxide-based insulating film is used as a gate insulating film or aprotection film.

[0213] (q) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a step of forming an oxide-basedinsulating film (silicon oxide film, silicon oxinitride film, or thelike) by performing high temperature thermal oxidation in an oxidizingatmosphere (air, oxygen, ozone, steam, NO, N₂O, or the like) of apolycrystalline or a single crystalline semiconductor thin-film, whichmay or may not contain at least one Group IV element such as tin, whichis formed on a high strain point glass by flash lamp annealing, andwhich is provided with a reflection-reducing, protective, insulatingfilm, wherein this oxide-based insulating film is used as a gateinsulating film or a protection film.

[0214] (r) A method for manufacturing a semiconductor thin-film or asemiconductor device, which comprises a step of modifying at least oneof an insulating film and a polycrystalline or a single crystallinesemiconductor thin-film, which may or may not contain at least one GroupIV element such as tin, formed by flash lamp annealing by heat treatment(steam annealing) at a temperature in the range of room temperature to astrain point of a substrate in an atmosphere containing water vapor at apartial pressure of 13.33 Pa to a saturated vapor pressure.

[0215] In this method, in order to modify the insulating film byneutralizing positive charges caused by defects or impurities in theinsulating film thus formed so as to make a flat band voltage at thenegative side to be closer to 0 V side, heat treatment (steam annealing)is performed at a temperature in the range of room temperature to thestrain point of the substrate in an atmosphere containing water vapor ata partial pressure of 13.33 Pa to a saturated vapor pressure. In thismethod, in consideration of a material and size of the substrate, andfilm thicknesses, film qualities, and the like of the insulating filmand the polycrystalline or the single crystalline semiconductorthin-film, a heating time in the range of, for example, 10 to 60minutes, is determined.

[0216] Next, preferred embodiments of the present invention will bedescribed in more detail.

[0217] First Embodiment

[0218] Referring to FIGS. 1 to 33, a first embodiment of the presentinvention will be described.

[0219] In this embodiment, the present invention is applied to a topgate type polycrystalline silicon CMOS (Complementary MOS) TFT.

[0220] <Catalytic CVD Method and Apparatus therefor>

[0221] A catalytic CVD method used for this embodiment will first bedescribed. In the catalytic CVD method, reacting gases composed of ahydrogen-based carrier gas and a source gas such as a silane gas arebrought into contact with a heated catalyst such as tungsten so as toimpart high energy to radicals depositing species, precursors thereof,hydrogen-based active species such as activated hydrogen ions, andsubsequently, a low-crystallization semiconductor thin-film such asmicrocrystalline silicon containing amorphous silicon is deposited on asubstrate by vapor-phase growth.

[0222] This catalytic CVD may be performed by using an apparatus asshown in FIGS. 5 and 6.

[0223] According to this apparatus, a gas composed of a hydrogen-basedcarrier gas and a source gas 40 (in addition, when necessary, a dopinggas such as B₂H₆, PH₃, or SnH₄ are contained) such as hydrogenatedsilicon (such as, monosilane) is supplied to a film-forming chamber 44from a supplying pipe 41 via an inlet (not shown) of a shower head 42.Inside the film-forming chamber 44, there are provided a susceptor 45for holding a substrate 1 such as glass, the shower head 42 havingsuperior heat resistance (material desirably having a melting pointequivalent to or higher than that of a catalyst 46), the catalyst 46such as tungsten in the form of, for example, spiral, and a shutter 47capable of opening and closing. In addition, although not shown in thefigure, magnetic shielding is provided between the susceptor 45 andfilm-forming chamber 44, and the film-forming chamber 44 is provided atthe back of a front chamber in which pre-process is performed and isevacuated by turbo-molecular pump or the like via a valve.

[0224] In addition, the substrate 1 is heated by heating means, such asheating wires, provided in the susceptor 45, and the catalyst 46 isheated to, for example, the melting point or less (in particular, 800 to2,000° C., and in the case of tungsten, approximately 1,600 to 1,800°C.) as a resistance wire and is activated. Both ends of the catalyst 46are connected to a DC or an AC power supply 48 for catalyst, and thecatalyst is heated to a predetermined temperature by electrical powersupplied by this power supply.

[0225] In order to perform the catalytic CVD method, when the apparatusis in the sate shown in FIG. 5, the degree of vacuum inside thefilm-forming chamber 44 is evacuated to 1.33×10⁻⁴ to 1.33×10⁻⁶ Pa, 100to 200 sccm of, for example, a hydrogen-based carrier gas is suppliedtherein, the catalyst is heated to a predetermined temperature foractivation, and the source gas 40 (and, when necessary, including anappropriate amount of doping gas such as B₂H₆ or PH₃) composed of 1 to20 sccm of hydrogenated silicon (such as monosilane) is supplied fromthe supplying pipe 41 via the inlet 43 of the shower head 42 so that thegas pressure is set to 0.133 to 13.3 Pa, for example, 1.33 Pa. In thesesteps, as the hydrogen-based carrier gas, a gas composed of hydrogen andan appropriate amount of an inert gas, such as hydrogen, hydrogen+argon,hydrogen+helium, hydrogen+neon, hydrogen+xenon, or hydrogen+krypton, maybe used (hereafter, the same as above).

[0226] Next, as shown in FIG. 6, the shutter 47 is opened, at least apart of the source gas 40 is brought into contact with the catalyst 46so as to be catalytically decomposed, and by a catalytic decompositionreaction or/and thermal decomposition reaction, clusters (that is,depositing species, precursors thereof, hydrogen-based radicals, and thelike) of reactive species, such as ions or radicals of silicon, having ahigh energy are formed. Reactive species 50, such as ions, radicals, orthe like, thus formed are formed into a predetermined film, such asmicrocrystalline silicon containing amorphous silicon, at high energy byvapor-phase growth on the substrate 1 at a temperature of 200 to 800° C.(for example, 300 to 400° C.).

[0227] Without generating plasma, since high energy is applied to thereactive species by the catalytic effect of the catalyst 46 and thermalenergy thereof, the source gas can be efficiently converted intoreactive species, and deposition can be uniformly performed on thesubstrate 1 by thermal CVD.

[0228] In addition, even when a substrate temperature is decreased,since energy of depositing species is high, a desired high quality filmcan be obtained. Accordingly, the substrate temperature can be furtherdecreased, a large size and inexpensive insulating substrate (a lowstrain point glass substrate, such as borosilicate glass oraluminosilicate glass, or a heat resistant resin substrate such aspolyimide) can be used, and from this point of view, cost reduction canalso be realized.

[0229] In addition, since plasma is not generated, it is naturallyunderstood that there have been no damages caused by plasma, the filmthus formed has a low stress, and in addition, compared to a plasma CVDmethod, a significantly simple and inexpensive apparatus can berealized.

[0230] In this case, operation can be performed under reduced pressure(for example, 0.133 to 1.33 Pa) and atmospheric pressure; however,compared to a reduced-pressure apparatus, a simple and inexpensiveatmospheric apparatus can be realized. In addition, by using thisatmospheric apparatus, compared to the case of conventional atmosphericCVD, a high quality film having superior density, uniformity, andadhesion can be obtained. In addition, in the case described above,since throughput of the atmospheric type is larger than that of thereduced-pressure type, the productivity is high, and as a result, costreduction can be achieved.

[0231] In the catalytic CVD described above, although the substratetemperature is increased by radiation heat of the catalyst 46, a heaterfor heating the substrate or cooling means 51 therefor may be providedwhen necessary, as described above. In addition, the catalyst has aspiral shape (in addition to this, a mesh, a wire, or a porous plate mayalso be used); however, a plurality of catalysts (for example, two tothree catalysts) is preferably provided in the gas flow direction so asto increase a contact area with the gas. In this CVD, since thesubstrate 1 is disposed on the bottom surface of the susceptor 45 andabove the shower head 42, particles generated in the film-formingchamber 44 do not fall on the substrate 1 and adhere to the film formedthereon.

[0232] <Flash Lamp Annealing and Apparatus therefor>

[0233]FIG. 7 shows an apparatus (annealer) for performing flash lampannealing by way of example. According to this, in an external housing200 for blocking emission light, an internal housing 201 (both housingsare purged with N₂) similar to the above is placed, a plurality of flashlamps 203, for example 10 lamps, enclosing a xenon gas or the like arecontained in the internal housing as a source of ultraviolet rays, andin addition, at the rear side thereof, a reflecting mirror 204 isprovided to enhance the emission intensity. In addition, by using acondensing uniformer (not shown in this figure), which is composed oflenses, mirrors, and the like, and which is provided between the lamps203 and the insulating substrate 1 (provided with a low-crystallizationsilicon thin-film), emission light may be condensed and homogenized intoa strip shape {for example, (500 to 600 mm)×(1 to 10 mm)}, a rectangularshape {for example, (10 to 100 mm)×(200 to 300 mm)}, a square shape (forexample, 100×100 mm), or circular shape (for example, 100 to 300 mm indiameter) for flash emission so as to decrease variation in emissionintensity and improve productivity by increases in fusion efficiency andthroughput. The substrate 1 is heated beforehand to a strain temperaturethereof or less by the heater 209 in the susceptor 208. The reflectingmember (reflecting mirror or the like) 204 may be provided with minuteirregularities on the surface thereof so as to uniform the illuminanceof reflected light by diffused reflection.

[0234] In addition, an IR-reducing or an IR-blocking filter 205 whichreduces or blocks at least infrared rays, such as a color filter glass(IR-absorbing filter) containing an IR-adsorbing material, such aspowdered copper, powdered iron, phosphoric acid, or the like; a coldmirror/cold filter coated with an IR-reflecting film such as an ITOfilm; or a filter (such as an IR-adsorbing filter coated with anIR-reflecting filter) formed by combining both materials described abovewith each other, may be provided between the lamps 203 and theinsulating substrate 1 so as to suppress increase in substratetemperature. The rear surface of the housing 201 may be controlled by,for example, cooling water pipes 207 in which a circulating coolingmedia flows so that the temperature is not unnecessarily increased.Accordingly, the reflecting functions of the reflecting plate 204 may bemaintained, and the light emission of the lamps may be stabilized.

[0235] In the lamp 205, as described below, when a high-voltage pulsegenerated by a flash discharge mechanism is applied, dielectricbreakdown of a gas such as xenon enclosed in the lamp occurs in amoment, electrical energy stored in a capacitor is emitted thereby in anextremely short time (in the range of microseconds to milliseconds), andat this time, flash by intensive arc discharge is emitted. This flash isabsorbed in a low-crystallization silicon thin-film and is convertedinto heat, and the silicon thin-film is fused.

[0236] In the step described above, light 210 emitted from the lamp 205has, for example, a spectral distribution shown in FIG. 8 and has awavelength having an emission intensity corresponding to a absorptionwavelength (ultraviolet region, approximately 400 nm or less) of thelow-crystallization silicon. In addition, the spectrum of the emissionlight 210 may be controlled by, for example, cutting a long wavelengthcomponent; however, when a long wavelength component to some extent isincluded, the substrate is heated by this wavelength component, and as aresult, large grain size may be formed due to slow cooling in somecases.

[0237] For example, FIGS. 25 and 26 are SEM (scanning electronmicroscope) pictures of a polycrystalline silicon thin-film formed byflash lamp annealing according to the present invention, and it isunderstood that large polycrystalline silicon grains having a size ofseveral micrometers described above are present. These pictures will bedescribed later in detail.

[0238] There are two reflecting mirrors 204, i.e., for example, aconcave type (A) and a flat type (B) as shown in FIG. 9, the former issuitable for performing flash emission in a strip form (improvement inilluminance) via a condensing lens 211, and the latter is suitable forperforming flash emission having, for example, a large square orrectangular area (improvement in uniformity) via a light uniformer(light homogenizer) 212. In this case, when necessary, light may beemitted in a predetermined direction via the IR-reducing or theIR-blocking filter. In addition, this light uniformer (light homogenizeror the like) may be coated with an IR-reflecting film.

[0239] For example, when flash lamp annealing is performed for the glasssubstrate 1 having a size of 1,000 mm×1,000 mm, there are methods (1) to(3) described below, and among these, a suitable method may beoptionally selected.

[0240] (1) As shown in FIG. 10 (1), as in the example shown in FIG. 7,simultaneous flash emission is performed once or repeatedly as requiredfor an entire large area of 1,000 mm×1,000 mm.

[0241] (2) As shown in FIG. 10 (2), the substrate 1 is fixed, flashemission light 210, which is condensed and homogenized to form a squareshape of 200 mm×200 mm, is scanned once or repeatedly as required in thesame region by a galvanometer scanner, and in addition, when necessary,flash emission is performed by overlap scanning.

[0242] (3) As shown in FIG. 10 (3), the position of flash emission isfixed in which flash emission light is condensed and homogenized to forma square shape of 200 mm×200 mm, the substrate 1 is precisely moved inthe X-Y direction in a step & repeat manner, flash emission is performedonce or repeatedly as required in the same region, and in addition, whennecessary, flash emission is performed by overlap scanning.

[0243] In addition, when flash emission is performed by overlap scanningand in a step & repeat manner, in order to decrease variation incrystallinity caused by crosstalk of flash emission light emitted to anadjacent region, an intercepting plate inhibiting light leakage in thelateral direction is preferably provided so that the distance betweenthe substrate and a lamp house (housing) or emission surface of a vacuumcontainer is decreased (for example, 10 mm or less) as small aspossible.

[0244] In addition, this flash lamp annealing conditions (emission lightwavelength of a lamp, emission intensity, emission time, cooling rate,and the like) may be appropriately optimized in consideration of thethickness of a low-crystallization silicon, a heat resistant temperatureof a glass substrate, and a grain size (carrier mobility) to beobtained. In addition, in flash lamp annealing, in order to form auniform crystalline film by a constant and stable substrate temperature,to reduce stresses in a crystalline film and a substrate, and todecrease lamp emission power, the glass substrate 1 is preferably heatedby the heater 209, an infrared lamp (halogen lamp), or the like to astrain point of the substrate 1 or less, for example, in the range ofroom temperature to 500° C., and preferably, in the range of 300 to 400°C.

[0245] In addition, as the ultraviolet lamp 203 which can be used in thepresent invention, light emission is preferably performed in a flashingmanner and repeatedly, and for example, xenon lamps, xenon-mercurylamps, xenon-krypton lamps, krypton lamps, krypton-mercury lamps,xenon-krypton-mercury lamps, and metal halide lamps may be used. As theflash discharge mechanism which enables a lamp emit light in a flashingmanner, as shown in FIG. 12, for example, a discharge lamp circuit isformed of a DC power supply 214, a capacitor C for storing charges, aninductance L formed of an inductance of a wire between the lamp powersupply 214 and the lamp 203, an internal inductance of the capacitor C,and an inductance for adjusting pulse width, and the like.

[0246] For example, in the case in which a lamp having the same shape isused, when a capacitor is charged at a higher charging voltage and isthen discharged, a voltage peak value in discharging is increased, andas a result, spectral intensity in the ultraviolet region at awavelength of 400 nm or less is relatively increased. In addition, inthe case in which the charging voltage is constant, with decrease ininductance, ⅓ pulse width is decreased, the peak value of a dischargecurrent waveform is increased, and as a result, spectral intensity inthe ultraviolet region at a wavelength of 400 nm or less is relativelyincreased.

[0247] In order to facilitate the formation of a large grain size(polycrystallization having higher carrier mobility) and the formationof single crystal by graphoepitaxial or heteroepitaxial growth, sinceslow cooling is preferably performed after silicon is fused, a flashtime (pulse width) and a peak value in flash lamp annealing, andrepeating speed and frequency of lamp emission are optionallycontrolled. In particular, since the better result is obtained withincrease in ⅓ pulse width, the ⅓ pulse width is, for example, 1millisecond or more, and preferably, 1.5 milliseconds or more. Inaddition, it is preferable that the ⅓ pulse width be optionally changedin accordance with a manufacturing method for a low-crystallizationsemiconductor thin-film, the thickness thereof, and the like.

[0248] In addition, the configuration is formed so that the peak valueand the pulse width of a charging current flowing through the lamp 203,and the repeating speed and the frequency of lamp emission can beoptionally controlled. In this case, as a method for connecting lamps,for example, the methods described below may be optionally used.

[0249] (1) as shown in FIG. 12 (1), two lamps 203 connected in seriesare connected to a corresponding lamp power supply 214, and four lampsin total are synchronized in parallel so as to emit light.

[0250] (2) as shown in FIG. 12 (2), each lamp 203 is connected to acorresponding lamp power supply 214, and the lamps simultaneously emitlight.

[0251] (3) as shown in FIG. 12 (3), lamps 203 connected in series areconnected to one lamp power supply 214, and the lamps simultaneouslyemit light.

[0252] As described above, when a plurality of lamps is used, and lightis emitted by synchronizing the plurality of lamps, the efficiency isincreased. In general, it is preferable that a plurality of lamps besynchronously triggered by using a trigger circuit (not shown) thatenables the lamps emit light so as to simultaneously emit light. When ahigh-voltage pulse of, for example, ten and several kilovolts is appliedby a trigger circuit via a trigger electrode, a thin streamer is formedalong the trigger electrode in a xenon gas enclosed in a light-emittingtube, dielectric breakdown occurs locally, and main discharge growsalong this part (in light emission by a simmer method, triggerelectrodes are not provided).

[0253] For example, in a flash lamp structure shown in FIG. 13(1), forexample, a pair of electrodes 216 and 217 is disposed to oppose eachother in the vicinities of both ends of a straight light-emitting tube215 having a diameter of 10 mm and a length of 150 mm, a triggerelectrode assembly such as a trigger wire 218 is disposed in the formof, for example, a coil wound around the tube, on the external wall ofthe light-emitting tube. In addition to this structure, as shown in FIG.13(2), the structure may be formed in which a pair or pairs ofelectrodes 216 and 217 are disposed so as to oppose each other in thevicinities of both ends of a parallel plate light-emitting tube 219having, for example, a length of 150 mm, a width of 100 mm, and a heightof 10 mm, and a trigger electrode thin-film pattern (or a triggerelectrode assembly) 220 composed of a transparent conductive film (ITO(Indium Tin Oxide), ZnO, or the like) is provided on the externalsurface of the light-emitting tube. In this case, the uniformity ofilluminance of flash emission light may be improved by processing(blast, etching, or the like) the wall surface (inside, outside, or bothsides) to form minute irregularities thereon. In addition, in the caseof the parallel plate light-emitting tube, it is preferable that theanodes 216, the cathodes 217, and the trigger metal electrodes (or atrigger electrode metal pattern) 220 be disposed so that the distancesbetween anodes, between cathodes, and between the trigger metal wiresare equivalent to each other.

[0254] Since the parallel plate (rectangular parallelepiped)light-emitting tube 219 described above has the structure in which thepair or the pairs electrodes 216 and 217 are disposed so as to opposeeach other in the vicinities of both ends of the parallel platelight-emitting tube having, for example, a length of 150 mm, a width of100 mm, and a height of 10 mm, and the trigger electrode assembly (or atrigger electrode thin-film pattern) 220 is provided on the externalwall of the light-emitting tube, with increase in flash emission area,the illuminance of the flash emission light can be uniformed by improveddischarge uniformity. In addition, since the individual electrodes 216and 217 can be simultaneously or independently operated, when someelectrodes are destroyed, the other electrodes can be normally operated,and hence, advantages can be obtained in view of maintenance ofdischarge intensity, life, and cost. Furthermore, in the case of theparallel plate light-emitting tube and the straight light-emitting tube,the uniformity of illuminance of flash emission light can be improved byprocessing (blast, etching, or the like) the wall surface (inside,outside, or both sides) to form minute irregularities thereon.

[0255] In addition, when the external wall of the light-emitting tube isadditionally processed to have irregularities thereon, since theuniformity of illuminance of the flash emission light, adhesion of thetransparent conductive film, and the adhesion of the metal wire havingspring properties are improved, stable light emission and long life canbe ensured. For example, although the parallel plate light-emitting tube220 having a length of 150 mm, a width of 100 mm, and a height of 10 mmhas an emission area equivalent to that of a plurality of straightlight-emitting tubes (for example, 10 tubes) 150 mm long and 10 mm indiameter, since flash emission equivalent to or superior to that of thestraight light-emitting tubes can be performed at a lower cost as awhole, the efficiency is high, the cost is low, the exchange frequencyis low, and hence, cost reduction can be realized.

[0256] In this case, when the trigger wires formed by patterning atransparent electrode film or a metal film is provided in parallel atthe opposite surface side of the parallel plate light-emitting tube fromthe light exit side, variation in discharge among the pairs ofelectrodes can be decreased, and as a result, stable light emission andlonger life can be achieved.

[0257] When a reflecting member which is being cooled is provided at therear side of a light-emitting tube, the temperature is not increasedduring operation, functions of the reflecting member are not degraded,the lamp performance is stabilized, and the conditions inside thehousing are not degraded since undesired gases are not generated,whereby stable light emission and longer life can be achieved. In thiscase, the light-emitting tube and reflecting member may be air-cooledusing fans or the like or water-cooled by circulating pure water (orultrapure water).

[0258] <Continuous Process of Catalytic CVD (or Plasma CVD or the like)and Flash Lamp Annealing>

[0259] In order to prevent contamination and to improve productivity, itis preferable that the step of forming the low-crystallizationsemiconductor thin-film and the flash lamp annealing step becontinuously or sequentially performed in accordance with, for example,an in-line (continuous chamber) method (linear type or rotation type), amultiple chamber method, or a cluster method in an apparatus in whichmeans (plasma CVD, catalytic CVD, sputtering, or the like) and anannealer are provided.

[0260] The cluster method (1) or (2) described below is more preferable.

[0261] (1) For example, as shown in FIG. 14, a cluster type integratedapparatus may be an apparatus in which a step of forming alow-crystallization semiconductor thin-film in a CVD portion, a step ofcrystallizing the thin-film by flash lamp annealing in an annealerportion, a step of returning the annealed thin-film to the CVD portion,a step of forming a low-crystallization semiconductor thin-film on thisannealed thin-film, and a step of again crystallizing this thin-film byflash lamp annealing in the annealer portion are repeatedly performed.In FIG. 15(A), the sequence of this in-line method is shown.

[0262] (2) In addition, as shown in FIG. 16, a cluster type integratedapparatus may be an apparatus in which a step of forming asubstrate-protection film (a laminate of silicon oxide and siliconnitride, or the like) in a CVD-1 portion, a step of forming alow-crystallization semiconductor thin-film in a CVD-2 portion, a stepof adding a Group IV element in a ion doping/ion implanting portion whennecessary, a step of crystallizing the thin-film by flash lamp annealingin an annealer portion, and a step of forming a gate insulating film (asilicon oxide film or the like) in a CVD-3 portion are continuouslyperformed. In FIG. 15(B), the sequence of this in-line method is shown.

[0263] In the method described above, the laminate composed of siliconoxide and silicon nitride, or the like formed in the CVD-1 portion maybe used as a substrate-protection film of a top gate type MOSTFT or as abottom gate insulating, protection film of a bottom gate type MOSTFT,and the silicon oxide film, the laminate composed of silicon oxide andsilicon nitride, or the like formed in the CVD-3 portion may be used asa gate insulating film of a top gate type MOSTFT or as a protection filmof a bottom gate type MOSTFT.

[0264] In addition, the CVD described above may be catalytic CVD, plasmaCVD, or plasma CVD using TEOS, and instead of CVD, sputtering may beused. In this CVD process, it is preferable that plasma or catalytic AHAtreatment be performed before film formation. For example, before a filmis formed by plasma CVD, plasma AHA treatment is performed only byhydrogen-based carrier gas without using a source gas, contaminants(low-oxidation film, moisture, oxygen, nitrogen, carbon dioxide, or thelike) on the surface of a formed polycrystalline silicon thin-film areremoved by the effect of hydrogen-based active species (active hydrogenions or the like) thus formed so that the interface is cleaned, and thata remaining amorphous silicon component is also etched, thereby forminga polycrystalline silicon thin-film having high crystallinity.Subsequently, by using this underlayer as a seed, a low-crystallizationsilicon thin-film is grown on this clean interface of this underlayerand is then formed into a superior polycrystalline semiconductorthin-film having a large grain size or a single crystallinesemiconductor thin-film by the following flash lamp annealing.

[0265] In order to prevent oxidation and nitridation, flash lampannealing is preferably performed in a hydrogen or a hydrogen-based gasatmosphere under a reduced-pressure or in a vacuum. As the atmosphere,hydrogen or a mixture of hydrogen and an inert gas (argon, helium,krypton, xenon, neon, or radon) is used, and the gas pressure is in therange of 1.33 Pa to less than atmospheric pressure and is preferably inthe range of 133 Pa to 4×10⁴ Pa. The degree of vacuum is in the range of1.33 Pa to less than atmospheric pressure and is preferably in the rangeof 13.3 Pa to 1.33×10⁴ Pa. However, when an insulating protection film(silicon oxide film, silicon nitride film, silicon oxinitride film,laminated film composed of silicon oxide and silicon nitride, or thelike) is provided on the surface of a low-crystallization semiconductorthin-film, or when continuous operation is not performed, flash lampannealing may be performed in an air or a nitrogen atmosphere atatmospheric pressure.

[0266] Since catalytic CVD and flash lamp annealing can be performedwithout generating plasma, there has been no damage caused by plasma,the film thus formed has a low stress, and in addition, compared to aplasma CVD method, a simple and inexpensive apparatus-can be realized.

[0267] In addition, in the flash lamp annealing described above, variousmodifications described below may be made.

[0268] In flash emission of a xenon lamp in a air or in a nitrogenatmosphere at atmospheric pressure, as is so-called thunder, anunnecessary impulsive sound occurs in addition to flash used forcrystallization. Accordingly, as shading and noise-insulating measures,as shown in FIG. 17(A), the structure in which the lamps 203 arecontained in an air-tight vacuum container 201, and the lamps 203 andthe reflecting member 204 are fixed to the vacuum container 201 withsprings 230 therebetween is formed. In addition to the springs 230,shock-absorbing materials may also be used.

[0269] In this case, as shown in FIG. 17(B), the downward emission typevacuum container 201, which is a lamp house, is fixed, and flash isemitted while the substrate 1 provided with a low-crystallizationsilicon thin-film is moved in a precise step & repeat manner. Withrespect to a plurality of the lamp houses 201, flash emission may beperformed while the substrate 1 is moved in an in-line manner. Inaddition, the substrate is fixed, and while the downward emission typevacuum container 201 is moved in a precise step & repeat manner, flashemission may be performed.

[0270] However, in the case of an integrated apparatus such as a clustertype, since the lamp house composed of lamps, a reflecting member, andthe like and the substrate are contained in the same vacuum container,and flash emission is performed therein, the shading measure has beenmade, and an impulsive sound has also been suppressed from thebeginning.

[0271] In flash lamp annealing, in addition to flash emission performedat predetermined intervals, flash emission may be controlled in a timeinterval difference mode by using switching means.

[0272]FIG. 23 shows an example of a charge and discharge circuitconfiguration used for performing flash emission in a time intervaldifference mode by switching means as described above.

[0273] There are three ways of connecting xenon flash lamps 203.

[0274] (1) At least two lamps are connected to each other in series andare connected to a corresponding power supply.

[0275] (2) Each lamp is connected to a corresponding power supply.

[0276] (3) All lamps are connected in series and are connected to acommon power supply. In this case, a plurality of lamps simultaneouslyemits light when being synchronously triggered.

[0277] Subsequently, control is performed in a time interval differencemode as described below by switching means performing ON-OFF operation.

[0278] (1) When SW₁ is first turned on, a high-voltage pulse having apulse height of several to several tens of kilovolts is applied to atrigger electrode, and simultaneously, SW₁′ is cooperatively turned on.A streamer is formed on the inside wall of the flash lamp along thetrigger electrode, dielectric breakdown of a gas (xenon) enclosed in thelamp occurs in a moment along the streamer, electrical energy stored ina capacitor C₁ is emitted thereby in an extremely short time, and atthis time, intensive flash is emitted.

[0279] (2) After an elapse of a predetermined time, SW₂ and SW₂′ areturned on, and flash emission is performed by C₂.

[0280] (3) After an elapse of a predetermined, SW₃ and SW₃′ are turnedon, and flash emission is performed by C₃.

[0281] SW₁ and SW₁′, SW₂ and SW₂′, SW₃ and SW₃′ are turned offimmediately after flashing. Next, almost at the same time as thedischarge is complete, charging of a charging capacitor by a DC powersupply starts. The time required for charging relates to a time constantτ which is determined by the product of the charging capacitance andcharging current-suppressing resistance. This time constant τ and adischarge time t generally has the relationship represented by τ>>t. Inaddition, flash emission energy E in flash emission can be obtained bythe equation represented by E=(½)×C×V² (J) (where C is dischargingcapacitance (μF), and V is an applied voltage (V)).

[0282] As shown in FIG. 18(a), when one step & repeat movement isperformed at each flash emission, the glass substrate 1 to be irradiatedis divided into nine areas, and emission is performed in accordance withthe sequence shown in the figure for each area.

[0283] When one step & repeat movement is performed at each flashemission as described above, for example, the following (1) to (3) arethe conditions therefor.

[0284] (1) A low-crystallization silicon thin-film (50 nm thick) isformed on a glass substrate of 1 meter by 1 meter, and on the surface ofthe thin-film, a reflection reducing, protection silicon oxide film (10to 50 nm thick) is formed. In addition, islands are formed in theregions where active elements (MOSTFT, diode, or the like) and passiveelements (resistor, capacitor, or the like) are formed.

[0285] (2) The irradiation area of this glass substrate is divided intonine areas, and flash emission light having an emission area of 330mm×330 mm is emitted once for each area.

[0286] (3) A charging time for the charging capacitor and a step &repeat tact of the substrate are assumed to 20 seconds and less than 10seconds, respectively.

[0287] In this case, using the discharge circuit shown in FIG. 23, theoperations (a) to (d) described below are performed.

[0288] (a) A trigger switch SW₁ and the discharge switch SW₁′ areswitched from On to Off, and when one flash emission is performed on anirradiation area {circle over (1)} by the discharging capacitor C₁, thedischarging capacitor C₁ is simultaneously charged.

[0289] (b) Immediately after the above step, the substrate is moved sothat an irradiation area {circle over (2)} is placed at an irradiationposition, the trigger switch SW₂ and the discharge switch SW₂′ areswitched from On to Off, and when one flash emission is performed on theirradiation area {circle over (2)} by the discharging capacitor C₂, thedischarging capacitor C₂ is simultaneously charged.

[0290] (c) Immediately after the above step, the substrate is moved sothat an irradiation area {circle over (3)} is placed at the irradiationposition, the trigger switch SW₃ and the discharge switch SW₃′ areswitched from On to Off, and when one flash emission is performed on theirradiation area {circle over (3)} by the discharging capacitor C₃, thedischarging capacitor C₃ is simultaneously charged.

[0291] (d) Immediately after the above step, the substrate is moved sothat an irradiation area {circle over (6)} is placed at the irradiationposition, the trigger switch SW₁ and the discharge switch SW₁′ areswitched from On to Off, and when one flash emission is performed on theirradiation area {circle over (6)} by the discharging capacitor C₁, thedischarging capacitor C₁ is simultaneously charged.

[0292] The operations described above are repeated, thereby performingflash lamp annealing for the glass substrate of 1 meter by 1 meter.Accordingly, when the charging time of the discharging capacitor isshort, it is naturally understood that the productivity can be furtherimproved. However, the melting point of a low-crystallizationsemiconductor thin-film, for example, the melting point (approximately1,200° C., slightly changed by a film-forming method, such as CVD,sputtering, or the like) of an amorphous silicon film, is assumed toapproximately correspond to three fourths of the peak value P.Accordingly, when the peak value P is low, it may correspond to ⅘ pulsewidth or the like in some cases.

[0293] In flash emission used for conventional DVD bonding or the like,the peak value (P) of a discharge current and ⅓ pulse width or ½ pulsewidth have been controlled; however, in the present invention, in fusionand cooling of a low-crystallization semiconductor thin-film, forexample, a peak value over the melting point (approximately 1,200° C.)of an amorphous silicon film, and a long fusion and a cooling time aslong as possible are required to obtain a large grain size and highcrystallinity. Accordingly, in the present invention, the control of thepeak value (P) of the discharge current and the pulse width arepreferably performed as described below.

[0294] Conventional method: the peak value and the ⅓ pulse width (or the½ pulse width)

[0295] The present invention:

[0296] (1) the peak value and the ⅓ pulse width (or the ½ pulse width)

[0297] (2) the peak value and the ⅓ pulse width (or the ½ pulse width)and the ⅔ pulse width (or the ¾ pulse width)

[0298] (3) the peak value and the ⅔ pulse width (or the ¾ pulse width)

[0299] However, since the ¾ pulse width is in the vicinity of, forexample, the melting point of an amorphous silicon film, and when thepeak value is low, it may be changed to the ⅘ pulse width or the like.

[0300] The control of flash emission conditions are performed by controlof an applied voltage V and a charging capacitor C, which determineemission energy E=(½)CV²(J), the peak value determined by an inductor L,and the pulse width (time span) described below.

[0301] τ₁=⅓ pulse width is a time span between a point of ⅓ of the peakvalue on an ascending curve, starting from zero, of an input currentwaveform and to a point of ⅓ of the peak value on a descending curvethereof, and in the present invention, 1.5 milliseconds or more ispreferable. τ₂=½ pulse width is a time span between a point of ½ of thepeak value on an ascending curve, starting from zero, of an inputcurrent waveform and to a point of ½ of the peak value on a descendingcurve thereof, and in the present invention, 1.0 milliseconds or more ispreferable.

[0302] τ₃=⅔ pulse width is a time span between a point of ⅔ of the peakvalue on an ascending curve, starting from zero, of an input currentwaveform and to a point of ⅔ of the peak value on a descending curvethereof, and in the present invention, 0.8 milliseconds or more ispreferable.

[0303] τ₄=¾ pulse width is a time span between a point of ¾ of the peakvalue on an ascending curve, starting from zero, of an input currentwaveform and to a point of ¾ of the peak value on a descending curvethereof, and in the present invention, 0.5 milliseconds or more ispreferable.

[0304] In this embodiment, this ¾ pulse width is assumed to be in thevicinity of the melting point of a low-crystallization semiconductorthin-film.

[0305] In addition, when flash emission is repeatedly performed for thesame region, it is performed as shown in FIG. 19(b).

[0306] For example, when the melting point (although the melting pointof an amorphous silicon is slightly changed by film-forming conditions,it is approximately 1,200° C.) of an amorphous silicon is assumed tocorrespond to the ¾ pulse width, by discharge of C₁, the P (peak value)and a fusion time represented by τ₄₁ are maintained; by discharge of C₂performed just before time τ₄₁ elapses, a fusion time represented by τ₄₂is maintained; by discharge of C₃ performed just before time τ₄₂elapses, a fusion time represented by τ₄₃ is maintained; and after thefusion time as a whole represented by τ₀=τ₄₁+τ₄₂+τ₄₃ (for example,1.5=0.5+0.5+0.5 milliseconds) is maintained, crystallization occurswhile slow cooling (this sequence is shown below) is performed.Accordingly, in this case, C₁≧C₂≧C₃ is satisfied, and the relationshipof the applied voltages is represented by E₁≧E₂≧E₃.

[0307] SW₁/SW₁′ ON->OFF τ₄₁

[0308] Within 0.5 milliseconds SW₂/SW₂′ ON→OFF τ₄₂

[0309] Within 0.5 milliseconds SW₃/SW₃′ ON→OFF τ₄₃

[0310] In addition, as shown in FIG. 20, the discharge current waveformmay be variously modified in one flash emission.

[0311] The curve {circle over (1)} in the figure is equivalent to thatin FIG. 19 and is composed of a generally steep ascending waveform and arelatively steep descending waveform. In addition, by the adjustment ofthe discharge circuit (C, L, R, and the like), curve {circle over (2)}is composed of a gentle ascending and a gentle descending waveform, andby the effects of preheating and slow cooling, a high-crystallizationpolycrystalline semiconductor thin-film having a large grain size or asingle crystalline semiconductor thin-film are formed. Furthermore, bythe adjustment of the discharge circuit (C, L, R, and the like), curve{circle over (3)} is composed of a gentler ascending waveform than thatof the curve {circle over (2)} and a relatively steep descendingwaveform similar to that of the curve {circle over (1)}, and by theeffect of preheating (improvement in uniformity of crystallization), auniform polycrystalline or a single crystalline semiconductor thin-filmare formed.

[0312] Next, referring to FIG. 21, the case in which preheating isperformed by flash emission will be describe. By discharge of C₁,preheating time τ₃₁ (⅔ pulse width) is maintained; by discharge of C₂,fusion time τ₄₁ (¾ pulse width) is maintained; and by discharge of C₃,fusion time τ₄₂ (¾ pulse width) is maintained. In this case, C₁<C₂≧C₃ issatisfied, and the relationship of the applied voltages is representedby E₁<E₂≧E₃. By this preheating, the uniformity of crystallization isimproved, a polycrystalline or a single crystalline semiconductorthin-film having uniform properties is formed.

[0313] In the case described above, τ₃₁: a time span (pulse width)between a point at which a discharge current, which is increased fromzero due to discharge of the charging capacitor C₁, reaches a level inthe range of ⅔ to less than ¾ of ¾ (melting point) of the peak value inτ₄₁≅τ₄₂ and a point at which the discharge current is then decreased,without reaching the melting point, to the level in the range of ⅔ toless than ¾ mentioned above.

[0314] τ₄₁: a time span (pulse width) between a point at which adischarge current, which is increased from zero due to the discharge ofa charging capacitor C₂, reaches ¾ of the peak value and a point atwhich the discharge current is then decreased to ¾ mentioned above.

[0315] τ₄₂: a time span (pulse width) between a point at which adischarge current, which is increased from zero due to the discharge ofa charging capacitor C₃, reaches ¾ of the peak value and a point atwhich the discharge current is then decreased to ¾ mentioned above.

[0316] Referring to FIG. 22, the case in which slow cooling is performedby flash emission will be described. By discharge of C₁, fusion time τ₄₁is maintained; by discharge of C₂, post-baking time τ₃₂ is maintained,and by discharge of C₃, post-baking time τ₃₃ is maintained. Concerningτ₄₁ (¾ pulse width), and τ₃₂ and τ₃₃ (⅔ pulse width), C₁>C₂≧C₃ andE₁>E₂≦E₃ are satisfied. By this slow cooling, a polycrystallinesemiconductor thin-film having a large grain size and high crystallinityor a superior single crystalline semiconductor thin-film is formed.

[0317] In the case described above, τ₄₁: a time span (pulse width)between a point at which a discharge current, which is increased fromzero due to the discharge of a charging capacitor C₁, reaches ¾ (meltingpoint) of the peak value, and a point at which the discharge current isthen decreased to ¾ mentioned above.

[0318] τ₃₂: a time span (pulse width) between a point at which adischarge current, which is increased from zero due to the discharge ofa charging capacitor C₂, reaches a level in the range of ⅔ to less than¾ of ¾ (melting point) of the peak value in τ₄₁, and a point at whichthe discharge current is then decreased to the level in the range of ⅔to less than ¾ mentioned above.

[0319] τ₃₃: a time span (pulse width) between a point at which adischarge current, which is increased from zero due to the discharge ofa charging capacitor C₃, reaches a level in the range of ⅔ to ¾ of ¾(melting point) of the peak value in τ₄₁, and a point at which thedischarge current is then decreased to the level in the range of ⅔ to ¾mentioned above.

[0320] Next, in flash lamp annealing, as shown in FIG. 24, when thesurface of a low-crystallization semiconductor thin-film 7A is coveredwith an insulating protection film 235, such as a silicon oxide film, asilicon nitride film, a silicon oxinitride film, a laminated filmcomposed of silicon oxide and silicon nitride, or a laminated filmcomposed of silicon oxide, silicon nitride, and silicon oxide, and isthen processed by flash lamp annealing in this state, a desiredpolycrystalline silicon thin-film 7 is reliably formed in the casedescribed above. However, in the case in which a low-crystallizationsilicon thin-film is not covered, since fused silicon may be scattered,or silicon particle may remain due to surface tension, a polycrystallinesilicon thin-film may not be formed in some cases. In addition, in thestep described above, a polycrystalline silicon thin-film is easilyformed from an amorphous silicon thin-film formed by plasma CVD or thelike, and when crystalline nuclei (seed), such as an amorphous siliconthin-film containing microcrystals, or a microcrystalline siliconthin-film containing amorphous silicon formed by reduced-pressure CVD,catalytic CVD, or the like, are present, a polycrystalline siliconthin-film having a large grain size or a single crystalline siliconthin-film is easily formed.

[0321] Next, the Hall effect carrier mobility of polycrystalline siliconthin-films formed by flash lamp annealing of the present invention wasevaluated, and in addition, evaluation of polycrystalline grain sizes bySEM and crystallinity by Raman spectroscopy were also evaluated.

[0322] <Conditions for Preparing Sample A>

[0323] Substrate: Quartz glass 20×20×0.7 mm

[0324] Low-Crystallization Semiconductor Thin-film: Amorphous siliconfilm (200 nm thick) by RF plasma CVD

[0325] Conditions of Flash Lamp Annealing: Emission energy:

[0326] approximately 20 J/cm² (relative value); Applied voltage:approximately 2,500 V; ⅓ Pulse Width: 1.5 milliseconds; Distance betweena lamp and a substrate: 50 mm; Nitrogen atmosphere at atmosphericpressure; Substrate temperature: 350° C.

[0327] Hall Element: 5×5 mm, 2×2 mm, 1×1 mm; Al electrodes (measurementterminals) provided at four corners thereof

[0328] Ion Implantation and Activation Treatment: Phosphorus ion at 10keV; Dose rate: 3×10¹⁴ atoms/cm²; Annealing at 550 to 580° C. for 30minutes

[0329] <Principle of Hall Effect>

[0330] The Hall effect is a phenomenon in which when an electric fieldand a magnetic filed perpendicular to each other are applied to asample, carriers move in the direction perpendicular to both theelectric field and the magnetic field, and as a result, an electromotiveforce is generated. A Hall measurement is a measurement method usingthis effect, and a type of carrier in a sample, density (density ofholes or electrons), and mobility can be easily measured thereby.

[0331] <Hall Effect Measurement>

[0332] Apparatus: Bio-Rad HL5500 Hall System

[0333] Measurement Conditions: I-means: 10 μA DC, room temperature,

[0334] Magnetic field: 0.320 Tesla,

[0335] Targ. V: 20 mV

[0336] <Measurement Data>

[0337] Sheet Resistance Rs=619 Ω/cm², Resistivity R=0.0124 Ω·cm

[0338] Electron Impurity Concentration N 7.68×10¹⁸ atoms/cc

[0339] Hall Effect Electron Mobility μe=65.7 cm /V·sec

[0340] According to these results, compared to μe=40 to 45 cm²/V·secwhich is the Hall effect electron mobility of a polycrystalline siliconthin-film obtained by an XeCl excimer laser annealing method under thesame conditions as those described above, the Hall effect electronmobility of the polycrystalline silicon thin-film obtained by the flashlamp annealing of the present invention is that μe=65.7 cm²/V·sec, andis approximately 1.5 times that mentioned above. When this flash lampannealing conditions are optimized, a larger crystal grain and highercarrier mobility may be obtained.

[0341] In addition, in SEM observation (×5,000) shown in FIG. 25, it isunderstood that particles of sample A, which contain polycrystallinesilicon, are relatively large such as several micrometers.

[0342] Furthermore, as shown in FIG. 28, according to microscopicobservation by a Raman scattering spectroscopic method (Ar laser (awavelength of 514.53 nm), a beam diameter of 1 μm, compared with singlecrystalline silicon: hereinafter, the same as described above), sample Ahas crystallinity almost equivalent to that of single crystallinesilicon; however, due to slight different structure, such as grain size,grain boundary, stress, and the like, the Raman spectrum is slightlyshifted to a smaller wave number side (amorphous silicon side).

[0343] <Conditions for Preparing Samples B and C>

[0344] Substrate: Borosilicate Glass Substrate 20×20×0.7 mm

[0345] Low-Crystallization Semiconductor Thin-film: Amorphous

[0346] Silicon film (50 nm thick) by RF plasma CVD

[0347] Protective, Insulating Film: Silicon oxide film (50 nm thick)(however, a half of the protective, insulating is removed, a regioncovered with this silicon oxide film is used as sample B, and the otherregion without this silicon oxide film is used as sample C)

[0348] Conditions of Flash Lamp Annealing: Emission energy:approximately 20 J/cm² (relative value); Applied voltage: approximately2,500 V; ⅓ Pulse Width: 1.5 milliseconds; Distance between a lamp and asubstrate: 50 mm; Air atmosphere; Substrate temperature: 350° C.

[0349] According to SEM observation (×5,000) of sample B, as shown inFIG. 26, since the protective, reflection-reducing silicon oxide film isprovided thereon (see FIG. 24), and silicon fused in flash lampannealing is trapped between the protective, reflection-reducing siliconoxide film and the glass substrate and is crystallized using an optionalcrystal nucleus as a seed, a polycrystalline silicon thin-filmapproximately 50 nm thick having a large grain size of 3 to 8 μm isformed so as to have a dispersed domain structure.

[0350] In addition, as shown in FIG. 29, according to microscopicobservation by a Raman scattering spectroscopic method, in sample B(provided with the protective, reflection-reducing silicon filmthereon), a polycrystalline silicon thin-film having a large grain sizeof 3 to 8 μm is formed, and hence, a polycrystalline silicon thin-filmhaving crystallinity equivalent to that of a single crystalline siliconis obtained.

[0351] In addition, according to SEM observation of sample C, as shownin FIG. 27, since the protective, reflection-reducing silicon oxide filmis not provided thereon (see FIG. 24), a part of silicon fused in flashlamp annealing is scattered or is solidified in an optional shape due tosurface tension, and as a result, silicon particles (lumps) having asize of several ten micrometers are formed.

[0352] In addition, as shown in FIG. 30, according to microscopicobservation by a Raman scattering spectroscopic method, in sample C (noprotective, reflection-reducing silicon film is provided thereon), asilicon particle (lump) having an optional shape of several tenmicrometers is formed, and this silicon has crystallinity approximatelyequivalent to that of single crystalline silicon.

[0353] In addition, a Raman scattering spectroscopic method has thefollowing features. Measurement Principle: Inelastic scattering (Ramanscattering) light is detected when excited (laser) light irradiates amaterial. By spectroscopically measuring the change in wavelength ofexcited light when it interacts with various elementary excitations inthe material, various information on atoms, molecules, and electronstructures of the material is obtained. Features: Information of amaterial at a predetermined position (>1 μm in diameter) can be obtainedin a nondestructive manner. Information to be obtained: Information onthe symmetric property and the homogeneity of energy crystals of variouselementary excitations in a solid (crystalline and amorphous material)

[0354] In addition, as shown in FIGS. 28 and 29, in the obtained Ramanspectrum, a peak having asymmetrical broad shoulders is observed, andthis difference in shape reflects slight difference in structure such asgrain sizes, grain boundaries, stresses, and the like of a siliconthin-film and also has close relationship with electrical properties.Based on the relationship described above, conversely, by finding outthe conditions for obtaining an Si:TO-phonon peak having the mostsuitable shape for a polycrystalline silicon TFT, the process may beoptimized.

[0355] In addition, during crystallization of a low-crystallizationsemiconductor thin-film by flash lamp annealing, when annealing isperformed in a magnetic field, an electric field, or a magnetic fieldand an electric field, the crystal orientation of crystal grains may bealigned.

[0356] For example, when a magnetic field is applied, as shown in FIG.31, around the periphery of the vacuum container 201 in which the flashlamp apparatus and the substrate 1 are contained, permanent magnets 231or electromagnets 232 are provided, and flash lamp annealing isperformed in the magnetic field thus formed.

[0357] As described above, for example, when flash lamp annealing isperformed in a magnetic field for the low-crystallization siliconthin-film 7A, electron spins of silicon atoms of the silicon thin-film7A, which is once fused, interact with the magnetic field and arealigned in a predetermined direction, and when the silicon thin-film inthis state is solidified by cooling, the crystal orientations thereinare aligned. Since the crystal orientations in the film thuscrystallized are almost aligned, electron potential barriers of grainboundaries are decreased, and hence, carrier mobilities are increased.In this step, it is important that the crystal orientations be alignedin a predetermined direction, and in accordance with the structure ofthe outer-shell orbit of a silicon atom, the crystal may be alignedperpendicular or parallel to the obtained polycrystalline siliconthin-film 7. Since the crystal grains are aligned, irregularities on thesurface of a polycrystalline silicon thin-film are not formed, and thesurface of the thin-film is planarized. Accordingly, a good condition ofthe interface between the thin-film and a gate insulating film or thelike is obtained, and hence, the carrier mobilities are improved.

[0358] In addition, since the flash lamps 203 used for flash lampannealing in a magnetic field are contained in the vacuum container 201,the emission efficiency is superior, and hence, the particularadvantages of the flash lamp can be fully obtained.

[0359]FIG. 32 is a view showing the in which an electric filed by apower supply 233 is applied instead of the magnetic field, and inparticular, around the periphery of the vacuum container 201 in whichthe flash lamp apparatus and the substrate 1 are contained, electrodes234 are provided for applying a high-frequency voltage (a DC voltage orboth voltages), thereby performing flash lamp annealing in an electricfield.

[0360] In this step, electron spins of silicon atoms of thelow-crystallization silicon thin-film 7A, which is once fused, interactwith the electric field and are aligned in a predetermined direction,and when the silicon thin-film in this state is solidified by cooling,the crystal orientations therein are aligned in a predetermineddirection. Accordingly, as in the case of the magnetic field describedabove, the crystal grains are aligned in a predetermined direction, thecarrier mobilities are increased, and the irregularities on the surfaceare also decreased. In addition, the emission efficiency of the flashlamp 203 is also superior.

[0361]FIG. 33 is a view showing the case in which the magnetic field andthe electric field are simultaneously applied, and in this example,flash lamp annealing is performed on the condition that the magneticfield by the permanent magnets 231 (electromagnets may be used instead),provided around the periphery of the vacuum container 201 in which theflash lamp apparatus and the substrate 1 are contained, and the electricfield by the electrodes 234 which apply a high-frequency voltage (a DCvoltage or both voltages) are simultaneously applied.

[0362] In this step, electron spins of silicon atoms of thelow-crystallization silicon thin-film 7A, which is once fused, interactwith the magnetic field and the electric field and are aligned therebyin a predetermined direction, and when the silicon thin-film in thisstate is solidified by cooling, the crystal orientations therein arefurther sufficiently aligned in a predetermined direction by themultiplier effect of the magnetic field and the electric field.Accordingly, the crystal grains are more easily aligned in apredetermined direction, the carrier mobilities are further increased,and the irregularities on the surface are also further decreased. Inaddition, the emission efficiency of the flash lamp 203 is alsosuperior.

[0363] <Formation of Top Gate Type CMOSTFT>

[0364] Next, an example of formation of a top gate type CMOSTFT usingflash lamp annealing of this embodiment will be described.

[0365] First, as shown in FIG. 1(1), at least on a TFT-forming region ofthe insulating substrate 1 composed of, for example, borosilicate glass,aluminosilicate glass, quartz glass, crystallized glass, or the like, asubstrate-protection film 100, which is a laminate composed of aprotective silicon nitride film and a silicon oxide film formed byvapor-phase growth, such as plasma CVD, catalytic CVD, orreduced-pressure CVD (hereafter, the same as described above).

[0366] In the case described above, a glass substrate may be selected inaccordance with a process temperature for TFT formation.

[0367] The case at a low temperature of 200 to 500° C.: a glasssubstrate (for example, 500×600×0.5 to 1.1 mm thick), such asborosilicate glass or aluminosilicate glass, or a heat resistant resinsubstrate such as polyimide may be used.

[0368] The case at a high temperature of 600 to 1,000° C.: a heatresistant glass substrate (for example, 6 to 12 inches in diameter and700 to 800 μm thick), such as quartz glass or crystallized glass, may beused.

[0369] The protective silicon nitride film is formed for stopping Naions from a glass substrate; however, it is not necessary when syntheticquartz glass is used.

[0370] In addition, when catalytic CVD is used, an apparatus similar tothat shown in FIGS. 5 and 7 may be used; however, in order to protectthe catalyst from being oxidized, it is necessary that the catalyst beheated to a predetermined temperature (approximately 1,600 to 1,800° C.,for example approximately 1,700° C.) with supply of a hydrogen-basedcarrier gas and that, after the film formation, the supply of thehydrogen-based carrier gas be stopped when the catalyst is cooled to atemperature at which oxidation will not occur.

[0371] As the film-forming conditions, a hydrogen-based carrier gas(hydrogen, argon+hydrogen, helium+hydrogen, neon+hydrogen, or the like)is always supplied in a chamber, and the flow volume, pressure,susceptor temperature are controlled as described below.

[0372] Chamber Pressure: approximately 0.1 to 10 Pa, for example 1 Pa

[0373] Susceptor Temperature: 350° C.

[0374] Flow Volume of Hydrogen-Based Carrier Gas (when a mixed gas isused, hydrogen concentration is 80 to 90 mole %): 100 to 200 sccm

[0375] In addition, the silicon nitride film 50 to 200 nm thick isformed by the following conditions.

[0376] Hydrogen is used as a carrier gas, and as a source gas,monosilane (SiH₄) and ammonia (NH₃) are mixed together at an appropriateratio.

[0377] Flow Volume of H₂: 100 to 200 sccm, Flow Volume of SiH₄: 1 to 2sccm, and Flow Volume of NH₃: 3 to 5 sccm

[0378] In addition, the silicon oxide film 50 to 200 nm thick is formedby the following conditions.

[0379] Hydrogen is used as a carrier gas, and as a source gas,monosilane (SiH₄) and O₂ diluted with He are mixed together at anappropriate ratio.

[0380] Flow Volume of H₂: 100 to 200 sccm, Flow Volume of SiH₄: 1 to 2sccm, Flow Volume of O₂ diluted with He: 0. to 1 sccm

[0381] The film-forming conditions by RF plasma CVD are shown below.

[0382] The silicon oxide film is formed under the conditions in whichthe SiH₄ flow is 5 to 10 sccm, the N₂O flow is 1,000 sccm, the gaspressure is 50 to 70 Pa, the RF power is 1,000 W, and the substratetemperature is 350° C.

[0383] In addition, the silicon nitride film is formed under theconditions in which the SiH₄ flow is 50 to 100 sccm, the NH₃ flow is 200to 250 sccm, the N₂ flow is 700 to 1,000 sscm, the gas pressure is 50 to70 Pa, the RF power is 1,300 W, and the substrate temperature is 250° C.

[0384] Next, as shown in FIG. 1(2), by catalytic CVD or plasma CVD, thelow-crystallization silicon thin-film 7A doped with, for example, aGroup IV element such as tin at a concentration of 10¹⁷ to 10²²atoms/cc, or preferably, 10¹⁸ to 10²⁰ atoms/cc (doping may be performedin a CVD step or in an ion implantation step after film formation) isformed to have a thickness of 50 nm. However, tin doping is not alwaysnecessary (hereafter, the same as described above). Next, a protective,reflection-reducing silicon oxide film 10 to 30 nm thick is formed.

[0385] In this case, the apparatus shown in FIGS. 5 and 6 is used, alow-crystallization semiconductor thin-film, such as a tin-dopedlow-crystallization silicon thin-film, is formed by the catalytic CVDunder the conditions described below.

[0386] Film Formation of Microcrystalline Silicon Containing AmorphousSilicon by Catalytic CVD: hydrogen as a carrier gas and a mixture ofmonosilane (SiH₄) and hydrogenated tin (SnH₄) at an appropriate mixingratio are used for this film formation, in which the H₂ flow is 150sccm, the SiH₄ flow is 15 sccm, and the SnH₄ flow is 15 sccm. In thisstep, a tin-doped silicon thin-film at an optional n or p-type dopantconcentration may be formed by adding an appropriate amount of an n-typedopant, such as phosphorus, arsenic, or antimony, or a p-type dopantsuch as boron to a silane-based gas (silane, disilane, trisilane, or thelike) used as a source gas.

[0387] The case of n-type: PH₃ (phosphine), AsH₃ (arsine), SbH₃(stibine)

[0388] The case of p-type: B₂H₆ (diborane)

[0389] When the individual films are formed in the same chamber, while ahydrogen-based carrier gas is always supplied, and the catalyst isheated to a predetermined temperature so that the chamber is in astandby state, the following may be processed.

[0390] After a silicon nitride film having a predetermined thickness isformed by mixing monosilane and ammonia at an appropriate ratio, and thesource gases or the like used for this film formation are sufficientlyevaluated, a silicon oxide film having a predetermined thickness iscontinuously formed by mixing monosilane and O₂ diluted with He, and thesource gases or the like used for this film formation are sufficientlyevaluated. Subsequently, after a tin-doped microcrystalline siliconfilm, containing amorphous silicon and having a predetermined thickness,is continuously formed by mixing monosilane and SnH₄ at an appropriateratio, and the source gases or the like used for this film formation aresufficiently evaluated, a silicon oxide film having a predeterminedthickness is continuously formed by mixing monosilane and O₂ dilutedwith He. After the film formation, the supply of the source gases isstopped, the catalyst is cooled to a temperature at which any problemmay not occur, and the supply of the hydrogen-based carrier gas is thenstopped. In this step, the flow volume of a source gas for forming theinsulating film may be gradually decreased or gradually increased so asto form an insulating film having a gradient junction.

[0391] In addition, when the individual films are formed in thedifferent chambers, while a hydrogen-based carrier gas is alwayssupplied into each chamber, and-the catalysts are heated to apredetermined temperature so that each chamber is in a standby state,the following may be processed. After being transferred to a chamber A,a silicon nitride film having a predetermined thickness is formed bymixing monosilane and ammonia at an appropriate ratio. Next, after thefilm thus formed is transferred to a chamber B, a silicon oxide filmhaving a predetermined thickness is formed by mixing monosilane and O₂diluted with He at an appropriate ratio. Next, after the film thusformed is transferred to a chamber C, a tin-doped microcrystallinesilicon film, containing amorphous silicon and having a predeterminedthickness, is formed by mixing monosilane and SnH₄ at an appropriateratio. Next, after the film thus formed is transferred to the chamber B,a silicon oxide film is formed by mixing monosilane and O₂ diluted withHe at an appropriate ratio. After the film formation, the supply of thesource gases is stopped, the catalyst is cooled to a temperature atwhich any problem may not occur, and the supply of the hydrogen-basedcarrier gas is the stopped. In this step, the hydrogen-based carrier gasand the source gases for forming the individual films may be alwayssupplied into the individual chambers so that the chambers are in astandby state.

[0392] The conditions for forming a low-crystallization siliconthin-film by RF plasma CVD are that the SiH₄ flow is 100 sccm, the H₂flow is 100 sccm, the gas pressure is 1.33×10⁴ Pa, the RF power is 100W, and the substrate temperature is 350° C.

[0393] Next, as shown in FIG. 1(3), in a nitrogen atmosphere atatmospheric pressure, by flash emission 221 performed once or repeatedlyusing a xenon flash lamp (or is called pulsed xenon lamp), amicrocrystalline silicon thin-film containing amorphous silicon 7A isfused, and the polycrystalline silicon thin-film 7, having a thicknessof 50 nm thick and a large grain size, is formed by slow cooling. Inaddition, in accordance with the substrate size, the substrate is movedprecisely in a step & repeat manner or the like, and flash emission isperformed on a predetermined area of the substrate.

[0394] This flash lamp annealing may be performed using any apparatusamong those shown in FIGS. 7 to 13, and the annealing conditions areshown below by way of example.

[0395] Lamp: xenon flash lamp (20 xenon lamps having a diameter of 10 mmand an effective arc length of 200 mm)

[0396] Irradiation Area: one flash emission performed on an area havinga square shape of 200×200 mm in a step & repeat manner

[0397] Emission energy: approximately 20 j/cm² (relative value)

[0398] Distance between Lamp and Glass Substrate: 50 mm

[0399] Applied Voltage: approximately: 2.5 kV

[0400] ⅓ Pulse Width: 1.5 milliseconds

[0401] Substrate Temperature: 300 to 400° C.

[0402] In this flash lamp annealing, when a protection film, such as asilicon oxide film, a silicon nitride film, a silicon oxinitride film, alaminated film composed of silicon oxide and silicon nitride, or thelike, is present on the surface of the low-crystallization semiconductorthin-film, a silicon fused in annealing is not scattered, siliconparticles (lumps) are not-formed due to surface tension, and as aresult, a polycrystalline silicon thin-film is preferably formed. Inaddition, when necessary, by using an IR-reducing or an IR-blockingfilm, the crystallinity may be improved, and substrate damages may bedecreased; however, in this case, the emission energy must be increased.

[0403] In order to decrease the rise of substrate temperature and tofacilitate the crystallization, when flash lamp annealing is performedafter islands are formed on a low-crystallization silicon thin-film orare formed on a low-crystallization silicon thin-film covered with aprotective silicon oxide film, a superior polycrystalline siliconthin-film can also be obtained.

[0404] In addition, when this flash lamp annealing is performed underappropriate conditions after the regions of gate channels, sources, anddrains, which will be described later, are formed, in addition toimproved crystallization, an n-type or a p-type dopant (phosphorus,arsenic, boron, or the like) implanted into the regions of the gatechannels, sources, and drains is also activated, and hence, theproductivity may be improved in some cases.

[0405] Next, a MOSTFT having the polycrystalline silicon thin-film 7,which is used for the regions of the gate channels, sources, and drains,is formed.

[0406] That is, in the case of a high temperature process, as shown inFIG. 2(4), after a protective, reflection-reducing silicon oxide film isremoved by common photolithographic and etching techniques, and inaddition, islands are formed on the polycrystalline silicon thin-film 7,in order to optimize the threshold value (V_(th)) by dopantconcentration control in the channel region of an n-type MOSTFT, afterp-type MOSTFT portions are masked with a photoresist 9, p-type dopantions (such as boron ions) 10 are doped at a dose rate of, for example,5×10¹¹ atoms/cm² by ion implantation or ion doping so as to have anacceptor concentration of 1×10¹⁷ atoms/cc, thereby forming ap-conductive type polycrystalline silicon thin-film 11 from thepolycrystalline silicon thin-film 7.

[0407] Next, as shown in FIG. 2(5), in order to optimize the thresholdvalue (V_(th)) by dopant concentration control in the channel region ofthe p-type MOSTFT, the n-type MOSTFT portions are masked with aphotoresist 12 in this case, and n-type dopant ions (such as phosphorusions) 13 are doped at a dose rate of, for example, 1×10¹² atoms/cm² byion implantation or ion doping so as to have a donor concentration of2×10¹⁷ atoms/cc, thereby forming an n-conductive type polycrystallinesilicon thin-film 14 from the polycrystalline silicon thin-film 7.

[0408] Subsequently, as shown in FIG. 3(6), after a silicon oxide film(50 nm thick) 8 is formed for a gate insulating film by catalytic CVD orthe like, a phosphorus-doped polycrystalline silicon film 15 used for agate electrode material is formed by catalytic CVD, which is the samemethod as described above, with supply of 2 to 20 sccm of PH₃ and 20sccm of SiH₄ so as to have a thickness of, for example, 400 nm.

[0409] Next, as shown in FIG. 3(7), a photoresist 16 is formed so as tohave a predetermined pattern, the phosphorus-doped polycrystallinesilicon film 15 is patterned by using the photoresist described above asa mask into a gate electrode shape, and in addition, after thephotoresist 16 is removed, as shown in FIG. 3(8), a silicon oxide film17 having a thickness of 20 nm is formed by, for example, catalytic CVD.

[0410] Subsequently, as shown in FIG. 3(9), the p-type MOSTFT portionsare masked by a photoresist 18, an n-type dopant, such as phosphorusions 19, is doped at a dose rate of, for example, 1×10¹⁵ atoms/cm² byion implantation or ion doping so as to have a donor concentration of2×10²⁰ atoms/cc, thereby forming an n⁺-type source region 20 and drainregion 21 of the n-type MOSTFT.

[0411] Next, as shown in FIG. 4(10), the n-type MOSTFT portions aremasked by a photoresist 22, a p-type dopant, such as boron ions 23, isdoped at a dose rate of, for example, 1×10¹⁵ atoms/cm² by ionimplantation or ion doping so as to have an acceptor concentration of2×10²⁰ atoms/cc, thereby forming a p⁺-type source region 24 and drainregion 25 of the p-type MOSTFT. Subsequently, by performing annealing atapproximately 900° C. for approximately 5 minutes in an N₂ atmosphere,the dopant ions doped in the individual regions are activated so as tohave the dopant concentration as determined beforehand.

[0412] The gate, the source, and the drain are formed as describedabove; however, these may be formed by methods except those describedabove.

[0413] That is, in the case of a low temperature process, after the stepshown in FIG. 1(2), islands are formed on the polycrystalline siliconthin-film 7 so that p-type MOSTFT and n-type MOSTFT regions are formed.This process is performed by steps of removing the protective,reflection-reducing silicon oxide film by common photolithographic andetching techniques using a fluorinated etching solution, selectivelyremoving the microcrystalline silicon thin-film containing amorphoussilicon by plasma etching using CF₄, SF₄, or the like, removing thephotoresist using an organic solvent, and washing. Since thepolycrystalline silicon thin-film, which will be formed, is easilycracked by stresses generated when silicon is fused by abrupttemperature increase by flash emission in the following flash lampannealing and is then cooled, in order to decrease the rise of substratetemperature, the formation of islands is also an important point. Theaims of this island formation before lamp annealing are to facilitatecrystal growth of fused silicon by slow cooling due to decreased heatdissipation and to suppress unnecessary increase in substratetemperature while silicon is fused.

[0414] Next, in a manner similar to that described above, after flashlamp annealing is performed for the low-crystallization siliconthin-film 7A, the protective, reflection-reducing silicon oxide film isremoved. Subsequently, as in a manner similar to that described above,by using photoresist masks, an n-type dopant, such as phosphorus ions,is doped at a dose rate of 1×10¹² atoms/cm² in the p-type MOSTFT regionsby ion implantation or ion doping so as to have a donor concentration of2×10¹⁷ atoms/cc, and a p-type dopant, such as boron ions, is doped at adose rate of 5×10¹¹ atoms/cm² in the n-type MOSTFT regions so as to havean acceptor concentration of 1×10¹⁷ atoms/cc, so that the dopantconcentrations of the individual regions are controlled and that theV_(th)s are optimized.

[0415] Next, by common photolithographic technique, using photoresistmasks, the individual source and drain regions are formed. In the caseof an n-type MOSTFT, an n-type dopant, such as arsenic or phosphorusions, is doped at a dose rate of 1×10¹⁵ atoms/cm² by ion implantation orion doping so as to have a donor concentration of 2×10²⁰ atoms/cc, andin the case of a p-type MOSTFT, a p-type dopant, such as boron ions, isdoped at a dose rate of 1×10¹⁵ atoms/cm² so as to have an acceptorconcentration of 2×10²⁰ atoms/cc.

[0416] Subsequently, for activating the n-type and p-type dopants in thepolycrystalline silicon thin-film, by using flash lamp annealing havingemission energy lower than that for crystallization or RTA (RapidThermal Anneal) using an infrared lamp such as a halogen lamp,activation of the dopant ions in the gate channel region, and the sourceand the drain regions is performed by heat treatment at approximately1,000° C. for approximately 30 seconds. Subsequently (or before dopantactivation), a silicon oxide film is formed as a gate insulating film,and when necessary, a silicon nitride film and a silicon oxide film arecontinuously formed. That is, by catalytic CVD, a silicon oxide film 8having a thickness of 40 to 50 nm is formed by using a hydrogen-basedcarrier gas and monosilane mixed with O₂ diluted with helium at anappropriate ratio, a silicon nitride film 10 to 20 nm thick is formed,when necessary, by using a hydrogen-based carrier gas and monosilanemixed with NH₃ at an appropriate ratio, and in addition, a silicon oxidefilm 40 to 50 nm thick is further formed under the same conditions asdescribed above.

[0417] Next, in the high temperature process, as shown in FIG. 4(11), bycatalytic CVD equivalent to that described above, a silicon oxide film26 having a thickness of, for example, 50 nm is formed by supplying 150sccm of a hydrogen-based carrier gas, which is also used for the otherCVD processes, 1 to 2 sccm of O₂ diluted with helium, and 15 to 20 sccmof monosilane; a phosphine silicate glass (PSG) film 28 having athickness of, for example, 400 nm is formed by supplying 1 to 20 sccm ofPH₃, 1 to 2 sccm of O₂ diluted with helium, and 15 to 20 sccm ofmonosilane; and a silicon nitride film 27 having a thickness of, forexample, 200 nm is formed by supplying 50 to 60 sccm of NH₃ and 15 to 20sccm of monosilane.

[0418] Subsequently, as shown in FIG. 4(12), contact widow holes areformed at predetermined positions in the insulating film describedabove. That is, window positions for the gate, the sources, the drainelectrodes of the n-type MOSTFT and the p-type MOSTFT are formed by aphotoresist pattern using common photolithographic and etchingtechniques; the silicon nitride film for passivation is etched by plasmaetching using CF₄, SF₆, or the like; the silicon oxide film and the PSGfilm are etched using a fluorinated etching solution; and thephotoresist is removed by washing using an organic solvent or the like,thereby forming exposed gate, source, drain regions of the n-type MOSTFTand the p-type MOSTFT.

[0419] Next, an electrode material such as 1%-silicon-containingaluminum is formed on the entire surface including the individualcontact holes by sputtering at 150° C. so as to have a thickness of 1 μmand is then patterned to form a source or a drain electrode 29 (S or D)and a gate lead electrode or a wire 30 (G) of each of-the p-type MOSTFTand the n-type MOSTFT, thereby forming each top gate type MOSTFT. Next,hydrogenating treatment and sintering treatment is performed in aforming gas at 400° C. for 1 hour. In this step, by catalytic CVD,aluminum may be formed by supplying an aluminum compound gas (such asAlCl₃).

[0420] Instead of the formation of the gate electrode described above, afilm (100 to 500 nm thick) composed of a heat resistant metal such as aMo—Ta alloy is formed by sputtering over the entire surface, andsubsequently, the gate electrodes of the n-type MOSTFT and the p-typeMOSTFT may be formed by common photolithographic and etching techniques.

[0421] In addition, a liquid-phase growth of a fused silicon alloy andflash lamp annealing, applied to a method for manufacturing a top gatetype polycrystalline silicon CMOSTFT, will be described. First, afterthe substrate-protection film described above is formed, amicrocrystalline silicon layer, which may contain tin, containingamorphous silicon is (precipitated) grown (hereinafter, the case inwhich tin is contained will be described) by one of the methodsdescribed below, and subsequently, a low melting point metal film, suchas tin, provided thereon is removed.

[0422] The substrate is coated with a fused low melting point metal suchas tin that contains silicon and is then cooled.

[0423] The substrate is immersed into a fused low melting point metalsuch as tin that contains silicon and is then pulled out therefrom forcooling.

[0424] A low melting point metal film composed of, for example, tin thatcontains silicon is fused by heating and is then cooled.

[0425] A low melting point metal film composed of, for example, tin thatcontains silicon is formed on a silicon film and is then fused byheating followed by cooling.

[0426] A silicon film is formed on a low melting metal film composed oftin or the like and is then fuses by heating followed by cooling.

[0427] Next, islands are formed on the microcrystalline silicon layer,which may or may not contain tin, containing amorphous silicon so as todivide into the p-type MOSTFT portions and the n-type MOSTFT portions,and the dopant concentrations of the channel regions are controlled byion implantation or ion doping so as to optimize the V_(th) (theconditions are equivalent to those described above). Subsequently, thesources and the drains of the p-type MOSTFT portions and the n-typeMOSTFT portions are formed by ion implantation or ion doping (theconditions are equivalent to those described above).

[0428] Next, flash lamp annealing is performed to facilitate thecrystallization and to activate ions (the conditions are equivalent tothose described above). A silicon oxide film used as a gate insulatingfilm is continuously formed by catalytic CVD, and when necessary, asilicon nitride film and a silicon oxide film are continuously formed(the conditions are equivalent to those described above). The processeshereafter to be performed are the same as those described above. Inaddition, the method using this liquid-phase growth may be applied to abottom gate type, a dual gate type CMOSTFT or the like, which will bedescribed later, in a manner similar to that described above.

[0429] A method for manufacturing a top gate type polycrystallinesilicon CMOSTFT using flash lamp annealing performed for alow-crystallization silicon thin-film formed by sputtering will bedescribed. First, the substrate-protection film described above isformed by sputtering. That is, on the entire surface of an insulatingsubstrate, a silicon nitride film (50 to 200 nm thick) is formed bysputtering performed at an argon pressure of 0.133 to 1.33 Pa in avacuum using a silicon nitride target, and on the entire surface of thissilicon nitride film, a silicon oxide film (100 to 200 nm thick) isformed by sputtering performed at an argon pressure of 0.133 to 1.33 Pain a vacuum using a silicon oxide target.

[0430] Next, by sputtering performed at an argon pressure of 0.133 to1.33 Pa in a vacuum using a silicon target which may or may not contain0.1 to 1 at % of tin, an amorphous silicon film, which may or may notcontain tin, having a thickness of 50 nm is formed at least in the TFTforming regions of the insulating substrate.

[0431] Next, by sputtering performed at an argon pressure of 0.133 to1.33 Pa in a vacuum using a silicon oxide target, a silicon oxide filmhaving a thickness of 10 to 30 nm is formed.

[0432] Alternatively, by using one common silicon target, a siliconnitride film using an argon gas and a nitrogen gas (5 to 10 mole %), asilicon oxide film using an argon gas and an oxygen gas (5 to 10 mole%), an amorphous silicon film using an argon gas, and a silicon oxidefilm using an argon gas and an oxygen gas (5 to 10 mole %) may becontinuously deposited by sputtering to form a laminate.

[0433] Next, islands are formed on the amorphous silicon layer, whichmay or may not contain tin, so as to divide into the p-type MOSTFTportions and the n-type MOSTFT portions (the conditions are equivalentto those described in the vapor-phase growth). Subsequently, the gatechannels, the sources, and the drains are formed by ion implantation orion doping (the conditions are equivalent to those described in thevapor-phase growth).

[0434] Next, flash lamp annealing is performed for the amorphous siliconthin-film which may or may not contain tin. By this flash lampannealing, a polycrystalline silicon thin-film is formed, andsimultaneously, the n-type or the p-type dopant processed by ionimplantation of ion doping are activated, thereby achieving optimumdopant concentrations in the gate channel, the source, and the drainregions (flash lamp annealing conditions are equivalent to thosedescribed above). In addition, as is the case described above, it isnaturally understood that flash lamp annealing for crystallization andflash lamp annealing or RTA treatment for ion activation may beseparately performed.

[0435] Subsequently, a silicon oxide film is formed as a gate insulatingfilm, and when necessary, a silicon nitride film and a silicon oxidefilm are continuously formed. That is, by catalytic CVD, a silicon oxidefilm 40 to 50 nm, a silicon nitride film 10 to 20 nm, and a siliconoxide film 40 to 50 nm are continuously formed (the film formingconditions are equivalent to those described above).

[0436] The processes hereafter to be performed are the same as thosedescribed above. In addition, the method using the films formed bysputtering may be applied to a bottom gate type, a dual gate typeCMOSTFT or the like, which will be described later, in a mannerequivalent to that described above.

[0437] In addition, when the formation of the low-crystallizationsilicon thin-film and the flash lamp annealing, which are describedabove, are repeated as required, since a polycrystalline silicon thickfilm can be formed having a large grain size, which has qualities closeto those of single crystalline silicon having high crystallinity andhigh purity, this polycrystalline silicon thick film may be preferablyused for forming CCD area/liner sensors, bipolar LSIs, solar cells, andthe like, which are preferably formed from a thick film. That is, at afirst flash lamp annealing, a polycrystalline silicon thin-film having alarge grain size and having a thickness of, for example, 200 to 300 nmis formed. Next, by a second flash lamp annealing, on thepolycrystalline silicon thin-film described above, a polycrystallinesilicon thin-film having a large grain size and having a thickness of,for example, 200 to 300 nm is formed using the underlayer as a seed,thereby forming a polycrystalline silicon thin-film having a large grainsize and having a thickness of approximately 400 to 600 nm. By repeatingthe step described above as required, a polycrystalline silicon thickfilm having a laminated structure and having a thickness in the order ofmicrometers can be formed. This thick film is also included in theconcept of “polycrystalline silicon thin-film” of the present invention.

[0438] In the case of this laminate, since the underlyingpolycrystalline silicon thin-film having a large grain size is used as aseed at the following flash lamp annealing, and a polycrystallinesilicon thin-film having a larger grain size is sequentially formed onthe underlayer, a polycrystalline silicon thick film having a largegrain size can be formed in which polycrystalline silicon located closerto the top surface of this thick film has qualities close to those ofsingle crystalline silicon which has high crystallinity and high purity.Accordingly, in addition to MOSLSIs, this polycrystalline silicon thickfilm is preferably used for forming devices, such as CCD area/linersensors, bipolar LSIs, or solar cells, in which active and passiveelement regions are formed on the surface of the thick film.

[0439] [I] In addition, as described above, in the case in which flashlamp annealing is performed after the islands are formed, one of thetreatments (1) to (4) described below is preferably performed.

[0440] (1) In a low temperature process (A), an amorphous silicon filmprovided with a laminated film composed of silicon oxide (hereinafterreferred to as SiO₂) and silicon nitride (hereinafter referred to asSiN_(x)) is patterned, so that islands are formed. After polycrystallinesilicon is formed by flash lamp annealing, the SiN_(x) film is onlyremoved, and a SiO₂ film or a laminate composed of SiO₂ and SiN_(x) isthen formed, thereby forming a gate insulating film formed of the SiO₂film or the laminate of SiO₂, SiN_(x), and SiO₂. The low temperatureprocess is a process in which a low strain point glass such asborosilicate glass or aluminosilicate glass or a heat resistant resinsuch as polyimide is used for a substrate (hereinafter, the same asdescribed above). In addition, since being formed by a low temperaturefilm formation such as plasma CVD, the silicon nitride film is not idealSi₃N₄ and is represented by SiN_(x) (hereinafter, the same as describedabove).

[0441] (2) In a low temperature process (B), an amorphous silicon filmprovided with a SiO₂ (or SiN_(x)) film is patterned, so that islands areformed. After polycrystalline silicon is formed by flash lamp annealing,a SiO₂ (or SiN_(x)) film is removed, and a SiO₂ film or a laminatecomposed of SiO₂, SiN_(x), and SiO₂ is formed for a gate insulatingfilm.

[0442] (3) In a low temperature process (C), an amorphous silicon filmis patterned, so that islands are formed. After flash lamp annealing isperformed, a laminate composed of SiO₂, SiN_(x), and SiO₂ issubsequently formed for a gate insulating film.

[0443] (4) In a high temperature process (A), after an amorphous siliconfilm is patterned so that islands are formed, flash lamp annealing isperformed, and the surface of a polycrystalline silicon film is thenoxidized by thermal oxidation at a high temperature (1,000° C. for 30minutes, thereby forming a gate insulating film. The high temperatureprocess is a process in which heat resistant glass such as quartz glassor crystallized glass or ceramic is used (hereafter, the same asdescribed above).

[0444] [II] In addition, in the case in which flash lamp annealing isperformed before the islands are formed, one of the treatments (1) to(4) described below is preferably performed.

[0445] (1) In a low temperature process (D), an amorphous silicon filmprovided with a laminated film composed SiO₂ and SiN_(x) is processed byflash lamp annealing and is then patterned, so that islands are formed.After the process described above, the SiN_(x) film is only removed, anda SiO₂ film or a laminated film composed SiO₂ and SiN_(x) is then formedthereon, so that the SiO₂ film or the laminated film composed of SiO₂,SiN_(x), and SiO₂ is formed for a gate insulating film.

[0446] (2) In a low temperature process (E), an amorphous silicon filmprovided with a SiO₂ (or SiN_(x)) film is processed by flash lampannealing and is then patterned, so that islands are formed. After theprocess described above, the SiN_(x) film (or SiN_(x)) is removed, and aSiO₂ film or a laminated film composed SiO₂, SiN_(x), and SiO₂ is thenformed thereon, so that individual films are used for a gate insulatingfilm.

[0447] (3) In a low temperature process (F), an amorphous silicon filmis processed by flash lamp annealing and is then patterned, so thatislands are formed. After the process described above, a SiO₂ film or alaminated film composed SiO₂, SiN_(x), and SiO₂ is then formed thereon,so that individual films are used for a gate insulating film.

[0448] (4) In a high temperature process (B), an amorphous silicon filmis processed by flash lamp annealing and is then patterned, so thatislands are formed. Subsequently, a polycrystalline silicon film isthermally oxidized by thermal oxidation at a high temperature (1,000° C.for 30 minutes, thereby forming a gate insulating film.

[0449] In both [I] and [II], in the low temperature process, SiO₂ isformed by catalytic CVD, plasma CVD, plasma CVD using TEOS, lowtemperature and high pressure annealing (thermal oxidation is performedby a so-called subcritical water reaction or supercritical waterreaction in which steam is used at a temperature in the range of roomtemperature to not more than a strain point of the substrate in a highpressure container reliably used up to 30 MPa), or the like, and SiN_(x)is formed by catalytic CVD, plasma CVD, or the like. The hightemperature process forms a high quality SiO₂ film and a polycrystallinesilicon thin-film by thermally oxidizing a polycrystalline siliconthin-film using a high temperature thermal oxidation method as describedabove. Accordingly, polycrystalline silicon must be formed so that thethickness thereof is relatively large. In accordance with requiredproperties, in both the low temperature and the high temperatureprocesses, a reflection-reducing, protective, insulating film (SiO₂,SiN_(x), SiON, or the like) on the low-crystallization silicon thin-filmused in flash lamp annealing may be used as a gate insulating film aftercrystallization is performed by flash lamp annealing.

[0450] As described above, according to this embodiment, superioradvantages (a) to (j) described below can be obtained.

[0451] (a) By flash lamp annealing which can perform flash emission onceor repeatedly in an optionally short period of time in the range ofmicroseconds to milliseconds, high emission energy is given to alow-crystallization semiconductor thin-film such as low-crystallizationsilicon so that the semiconductor thin-film is heated and cooled to afusion, a semi-fusion, or a non-fusion state, and hence, apolycrystalline semiconductor thin-film such as a polycrystallinesilicon thin-film having a large grain size, high carrier mobility, andhigh quality, or a single crystalline semiconductor thin-film isobtained, whereby the productivity is significantly increased, andconsiderable cost reduction can be realized.

[0452] (b) In flash lamp annealing, by combining an optional number oflamps with a flash discharge mechanism therefor, for example, (1) theentire large area of 1,000 mm×1,000 mm can be simultaneously irradiatedonce or repeatedly as required with flash emission light, (2) flashemission light which is condensed and homogenized to have a squareemission area of 200 mm×200 mm is scanned by a galvanometer scanner, andwhen necessary, flash emission is performed by overlap scanning, or (3)under the conditions in which the emission position of flash emissionlight which is condensed and homogenized to have a square emission areaof 200 mm×200 mm is fixed, and a substrate is moved in a step & repeatmanner, flash emission is performed and, when necessary, is performed byoverlap scanning. As described above, since the substrate or flashemission light can be moved in an optional direction at an optionalspeed, heating and cooling rate can be controlled, an optional largearea of a low-crystallization silicon thin-film or the like can becrystallized in an extremely short time, and hence, significantly highproductivity and considerable cost reduction can be realized.

[0453] (c) Since flash emission light is condensed and homogenized tohave a strip, a rectangular, a square, or circular form and is thenemitted, the emission intensity, that is, fusion efficiency andthroughput, is improved, and variation in carrier mobility can bedecreased by improvement in uniformity of crystallized film properties.

[0454] (d) By repeating the method in which a film composed oflow-crystallization silicon or the like is formed on a film composed ofpolycrystalline silicon or the like previously crystallized by flashlamp annealing, and crystallization is again performed by flash lampannealing, a polycrystalline silicon film or the like, which has a largegrain size, high carrier mobility, and high quality, can be formedhaving a laminated structure and a thickness in the order ofmicrometers. Accordingly, in addition to MOSLSIs, high performance andhigh quality bipolar LSIs, CMOS sensors, CCD area/linear sensors, solarcells, and the like can be formed.

[0455] (e) Since adjustment of wavelength (change of an enclosed gas,use of an IR-reducing or an IR-blocking filter, change of dischargeconditions, and the like) and control of emission intensity, emissiontime, and the like in flash lamp annealing can be easily performed inaccordance with the film thickness of a low-crystallizationsemiconductor thin-film, a heat resistant temperature of a substratesuch as glass, and a desired grain size (carrier mobility), apolycrystalline silicon film or the like having high carrier mobilityand high quality can be reproducibly obtained at high productivity rate.

[0456] (f) Lamps used for flash lamp annealing, such as xenon lamps,xenon-mercury lamps, krypton lamps, krypton-mercury lamps, xenon-kryptonlamps, xenon-krypton-mercury lamps, and metal halide lamps, are muchinexpensive than an excimer laser oscillator of an excimer laserannealing apparatus using XeCl, KrF, or the like, have longer life, andrequire easier maintenance, and hence, significant cost reduction can beachieved by increase in productivity rate and reduction in running cost.

[0457] (g) Since a flash lamp annealing apparatus primarily composed offlash lamps and a discharge circuit has a simple structure compared tothat of an excimer laser annealing apparatus, it is inexpensive, andhence, cost reduction can be realized.

[0458] (h) Since excimer laser annealing performed by XeCl, KrF, or thelike uses a pulse oscillating laser in the order of nanoseconds, therehas been a problem of output stability, and hence, there have beenvariation in energy distribution in an irradiation area, variation inquality of obtained crystallized semiconductor films, and variation inelement performance between MOSTFTs. Accordingly, a method in whichexcimer laser pulse is emitted many times, such as 5 times or 30 times,is performed while a temperature of approximately 400° C. is applied;however, properties of crystallized semiconductor films and TFT elementsvary due to the emission variation, and the cost is increased bydecrease in productivity rate caused by decrease in throughput. Incontrast, in flash lamp annealing, as described in the above (b), sincethe entire large area of, for example, 1,000 mm×1,000 mm can besimultaneously irradiated with flash emission light using a pulse in therange of microseconds to milliseconds, variation in energy distributionin the irradiation area, variation in quality of obtained crystallizedsemiconductor films, and variation in element performance betweenMOSTFTs are small, and cost reduction can be realized due to highproductivity rate caused by high throughput.

[0459] (i) In particular, flash lamp annealing by intensive ultravioletrays, using an IR-reducing or an IR-blocking filter, can be performed ata low temperature (200 to 400° C.), a low strain point glass or a heatresistant resin substrate, which is inexpensive and can be formed into alarge size, may be used, and hence, reduction in weight and cost can beachieve.

[0460] (j) In addition to a top gate type MOSTFT, since apolycrystalline semiconductor film having high carrier mobility or asingle crystalline semiconductor film can be formed for a bottom gatetype, a dual gate type, and a back gate type MOSTFTs, high speed, highcurrent density semiconductor devices, electrooptic devices, and highlyefficient solar cells can be formed by using this high-performancesemiconductor films. For example, there may be mentioned siliconsemiconductor devices, silicon semiconductor integrated circuit devices,field emission display (FED) devices, silicon-germanium semiconductordevices, silicon-germanium semiconductor integrated circuit devices,silicon carbide semiconductor devices, silicon carbide semiconductorintegrated circuit devices, III-V and II-VI compound semiconductordevices, III-V and II-VI compound semiconductor integrated circuitdevices, polycrystalline or single crystalline diamond semiconductordevices, polycrystalline or single crystalline diamond semiconductorintegrated circuit devices, liquid crystal display devices,electroluminescent (organic or inorganic) display devices,light-emitting polymer display devices, light-emitting diode displaydevices, light sensor devices, CCD area/linear sensor devices, CMOSsensor devices, and solar cells.

[0461] Second Embodiment

[0462] <LCD Manufacturing Example 1>

[0463] In this embodiment, the present invention is applied to an LCD(liquid crystal display device) using a polycrystalline silicon MOSTFTformed by a high temperature process, and hereinafter, a manufacturingexample therefor will be described.

[0464] First, as shown in FIG. 34(1), in a pixel portion and aperipheral circuit portion, a substrate-protection film 100 (not shownin the figure, and hereafter, the same as described above) is formed onone major surface of a heat resistant substrate 61 (a strain point ofapproximately 800 to 1,100° C., and a thickness of 50 μm to severalmillimeters) composed of quartz glass or crystallized glass by thecatalytic CVD or the like described above, and on this protection film,a low-crystallization silicon thin-film 67A is formed by the catalyticCVD or the like described above. In addition, when necessary, aprotective, reflection-reducing silicon oxide film (10 to 30 nm thick)is formed (not shown in this figure).

[0465] Next, as shown in FIG. 34(2), the flash lamp annealing describedabove is performed for the low-crystallization silicon thin-film 67A,thereby forming a polycrystalline silicon thin-film 67 having athickness of, for example, 50 nm.

[0466] Next, as shown in FIG. 34(3), after the protective,reflection-reducing silicon oxide film is removed, by commonphotolithographic and etching techniques, the polycrystalline siliconthin-film 67 is patterned (island formation), so that active layers foractive elements, such as transistors and diodes, and for passiveelements, such as resistors, capacitors, or inductances, are formed. Theprocess performed hereinafter will be described about TFT manufacturing;however, it is naturally understood that the process be the same as thatfor forming the other elements.

[0467] Next, after ion implantation or ion doping is performed using apredetermined dopant such as boron or phosphorus, which are the same asdescribed above, in order to optimize the V_(th) by controlling dopantconcentrations in individual channel regions of the polycrystallinesilicon thin-film 67, as shown in FIG. 34(4), a silicon oxide film 68having a thickness of, for example, 50 nm used for a gate insulatingfilm is formed on the surface of the polycrystalline silicon thin-film67 by, for example, catalytic CVD, similar to that described above. Whenthe silicon oxide film 68 used for a gate insulating film is formed bycatalytic CVD or the like, the substrate temperature and the catalysttemperature are the same as those described above, and a oxygen gas flowof 1 to 2 sccm, a monosilane gas flow of 15 to 20 sccm, and ahydrogen-based gas flow of 150 sccm may be used.

[0468] Next, as shown in FIG. 35(5), as a gate electrode and a gate linematerial, for example, a Mo—Ta alloy having a thickness of, for example,400 nm is formed by sputtering, or a phosphorus-doped polycrystallinesilicon film having a thickness of, for example, 400 nm is formed bycatalytic CVD or the like, similar to that described above, bysupplying, for example, 150 sccm of a hydrogen-based carrier gas, 2 to20 sccm of PH₃, and 20 sccm of monosilane gas. In addition, by commonphotolithographic and etching techniques, the gate electrode materiallayer is patterned so as to form gate electrodes 75 and gate lines. Inthe case of the phosphorus-doped polycrystalline silicon film, after aphotoresist mask is removed, a silicon oxide film is formed on thephosphorus-doped polycrystalline silicon film 75 in O₂ atmosphere byoxidation treatment at, for example, 900° C. for 60 minutes.

[0469] Next, as shown in FIG. 35(6), a p-type MOSTFT portion is maskedwith a photoresist 78, an n-type dopant such as arsenic (or phosphorus)ions 79 is doped at a dose rate of, for example, 1×10¹⁵ atoms/cm² by ionimplantation or ion doping so as to have a donor concentration of 2×10²⁰atoms/cc, thereby forming a n⁺-type source regions 80 and drain region81 of the n-type MOSTFT.

[0470] Next, as shown in FIG. 35(7), n-type MOSTFT portions are maskedwith a photoresist 82, a p-type dopant such as boron ions 83 is doped ata dose rate of, for example, 1×10¹⁵ atoms/cm² by ion implantation or iondoping so as to have an acceptor concentration of 2×10²⁰ atoms/cc,thereby forming a p⁺-type source region 84 and drain region 85 of thep-type MOSTFT. Subsequently, by annealing in an N₂ atmosphere atapproximately 900° C. for approximately 5 minutes, the dopant ions dopedin the individual regions are activated so that the dopantconcentrations are controlled as determined beforehand. In addition, inorder to improve the switching properties, n⁻-type LDDs (Lightly DopedDrain) may be formed in the n-type MOSTFT portion in the display region.

[0471] Subsequently, as shown in FIG. 35(8), by catalytic CVD or thelike similar to that described above, a silicon oxide film having athickness of, for example, 50 nm is formed by supplying 150 sccm of ahydrogen-based carrier gas, which is also used for the other CVDprocesses, 1 to 2 sccm of O₂ diluted with helium, and 15 to 20 sccm ofSiH₄; a phosphine silicate glass (PSG) film having a thickness of, forexample, 600 nm is formed by supplying 1 to 20 sccm of PH₃, 1 to 2 sccmof O₂ diluted with helium, and 15 to 20 sccm of SiH₄; and a siliconnitride film having a thickness of, for example, 200 nm is formed bysupplying 50 to 60 sccm of NH₃ and 15 to 20 sccm of SiH₄, therebyforming a laminate, composed of insulating films, which is used for aninterlayer insulating film 86. However, the interlayer insulating filmmay also be formed by a method different from that described above.

[0472] Next, as shown in FIG. 36(9), contact widow holes are formed atpredetermined positions in the insulating film 86 described above, andan electrode material such as aluminum 1 μm thick is deposited over theentire surface including the individual contact holes at 150° C. bysputtering or the like and is then patterned, thereby forming a sourceelectrode 87 and a data line of the n-type MOSTFT in the pixel portion,and source electrodes 88 and 90 and drain electrodes 89 and 91 of thep-type MOSTFT and the n-type MOSTFT in the peripheral circuit portion,respectively. In this case, aluminum may be deposited by catalytic CVD.

[0473] Next, on the surface, an interlayer insulating film 92 composedof a silicon oxide film or the like is formed by CVD or the like, andhydrogenating and sintering treatment is performed in a forming gas at400° C. for 30 minutes. Subsequently, as shown in FIG. 36(10), a contacthole is formed in the insulating films 92 and 86 in the drain region ofthe n-type MOSTFT in the pixel portion, and for example, ITO (Indium-tinOxide: a transparent electrode material formed by doping tin into anindium oxide) is deposited over the entire surface by vacuum depositionand is then patterned, thereby forming a transparent pixel electrode 93connected to the drain region 81 of the n-type MOSTFT in the pixelportion. Subsequently, heat treatment (at 200 to 250° C. for 1 hour in aforming gas) is performed in order to decrease in contact resistance andimprove in ITO transparency.

[0474] As described above, an active matrix substrate is formed, andhence, a transmissive type LCD may be formed. As shown in FIG. 36(11),this transmissive type LCD has the structure in which on the transparentpixel electrode 93, an alignment film 94, liquid crystal 95, analignment film 96, a transparent electrode 97, and a counter substrate98 are laminated to each other.

[0475] The steps described above may also be applied to manufacturing ofa reflective type LCD. In FIG. 41(A), an example of this reflective typeLCD is shown, and in the figure, reference numeral 101 indicates areflection mirror formed of aluminum or the like which cover theinsulating film 92 having irregularities thereon, and this reflectionmirror is connected to a drain of a MOSTFT.

[0476] When a liquid crystal cell of this LCD is manufactured bydouble-side assembly (suitably applied to a medium and a large liquidcrystal panel of 2 inches or more), on element mounting surfaces of theTFT substrate 61 and the counter substrate 98 entirely covered with ITO(Indium Tin Oxide) electrode 97, alignment films 94 and 96 composed ofpolyimide are formed, respectively. These alignment film composed ofpolyimide are formed by roll coating, spin coating, or the like so as tohave a thickness of 50 to 100 nm and is then cured at 180° C. for 2hours.

[0477] Next, the TFT substrate 61 and the counter substrate 98 areprocessed by rubbing or optical alignment treatment. As a rubbing buffmaterial, there may be mentioned cotton, rayon, or the like, and cottonis reliably used in terms of buff leavings (litter), retardationproperties, and the like. Optical alignment is a non-contact alignmenttechnique for liquid crystal using linearly polarized ultraviolet lightemission. In alignment, in addition to rubbing treatment, a polymeralignment film may be formed by polarized or non-polarized light whichis diagonally incident (as the polymeric compound described above, forexample, a polymethyl methacrylate polymer having azobenzene may bementioned by way of example).

[0478] Subsequently, after washing, a common material and a sealingmaterial are applied to the TFT substrate 61 side and the countersubstrate 98 side, respectively. In order to remove rubbing buffleavings, washing is performed using water or IPA (isopropyl alcohol).The common material may be an acrylic, an epoxy acrylate, or anepoxy-based adhesive containing conductive fillers, and the sealingmaterial may be an acrylic, an epoxy acrylate, or an epoxy-basedadhesive.

[0479] A hat curable, ultraviolet curable, and ultraviolet and heatcurable type may be used; however, in view of bonding accuracy andworkability, a ultraviolet and heat curable type is preferably used.

[0480] Next, spacers are scattered at the counter substrate 98 side soas to secure a predetermined gap, and subsequently, the countersubstrate is bonded to the TFT substrate 61 at a predetermined position.After alignment marks on the counter substrate 98 side and alignmentmarks on the TFT substrate 61 side are precisely corresponded to eachother, the sealing material is pre-cured by ultraviolet irradiation, andthen heat curing is thoroughly performed.

[0481] Next, by a scribe and break method, single liquid crystal panelsformed of the TFT substrate 61 and the counter substrate 98 bondedthereto are formed.

[0482] Next, the liquid crystal 95 is injected in the gap between bothsubstrates 61 and 98, an inlet therefor is sealed with an ultravioletcurable adhesive, and subsequently, washing is performed using IPA. Anytype of liquid crystal may be used, and, for example, a high-speedresponse TN (twisted nematic) mode using nematic liquid crystal isgenerally used.

[0483] Next, by heating and rapid cooling, the liquid crystal 95 isoriented.

[0484] Next, flexible wire is connected to a panel electrode leadportion of the TFT substrate 61 by thermal compression bonding of ananisotropic conductive film, and a polarizer is further bonded to thecounter substrate 98.

[0485] When single-side assembly of a liquid crystal panel (suitablyused for a small liquid crystal panel of 2 inches or less) is used, asis the case described above, on element mounting surfaces of the TFTsubstrate 61 and the counter substrate 98, the alignment films 94 and 96formed of polyimide are formed, respectively, and both substrates areprocessed by rubbing or non-contact optical alignment treatment usinglinearly polarized ultraviolet rays.

[0486] Next, each of the TFT substrate 30 and the counter substrate 32is cut by dicing or a scribe and break method, and then washed withwater or IPA. The common agent and the sealing agent containing spacersare applied to the TFT substrate 61 and the counter substrate 98,respectively, and then both substrates are bonded together. Thesubsequent process may be carried out in accordance with those describedabove.

[0487] In the LCD described above, the counter substrate 98 is a CF(color filter) substrate in which a color filter layer (not shown) isprovided below the ITO electrode 97. Incident light from the countersubstrate 98 side is efficiently reflected by the reflecting film 93,and may be emitted from the counter substrate 98 side.

[0488] On the other hand, when the TFT substrate 61 is provided with acolor filter layer so as to serve as a TFT substrate having an on-chipcolor filter (OCCF) structure, the ITO electrode is bonded to the entiresurface of the counter substrate 98 (or the ITO electrode provided witha black mask is bonded to the entire surface).

[0489] In the case of a transmissive LCD, by the procedure describedbelow, the on-chip color filter (OCCF) structure and an on-chip black(OCB) structure can be formed.

[0490] That is, as shown in FIG. 36(12), an aluminum buried layer forthe drain electrode is formed after a window is formed in the insulatingfilm 86 composed of phosphine silicate glass and silicon oxide.Subsequently, individual colors R, G, and B composed of photoresist 99,which contains pigments dispersed therein and has a predeterminedthickness (1 to 1.5 μm), are formed in the corresponding segments andare then patterned by common photolithographic technique so that thecolors R, G, and B remain at predetermined positions (individual pixelportions) in the corresponding segments, thereby forming individualcolor filters 99(R), 99(G), and 99(B) (on-chip color filter structure).In this step, windows are formed at the drain portions. An opaqueceramic substrate or glass and heat resistant resin substrates having alow transmittance cannot be used.

[0491] Next, a shading layer 100′ used as a black mask is formed bypatterning metal on the color filter layer including contact holesextending to the drain of a display TFT. For example, a molybdenum film200 to 250 nm thick is formed by sputtering and is then patterned toform a predetermined shape covering the display MOSTFT for shading(on-chip black structure).

[0492] Next, a planarizing film 92 composed of a transparent resin isformed, and in addition, an ITO transparent electrode 93 is formed in athrough-hole provided in this planarizing film so as to be in contactwith the shading layer 100′.

[0493] As described above, by forming color filter 99 and a black mask100′ on the display array portion, the aperture ratio of the liquidcrystal display panel is improved, and a lower power consumption of adisplay module including a backlight can be realized.

[0494]FIG. 37 is a schematic view showing the entire active matrixliquid crystal display device (LCD) integrated with a driving circuitincluding the top gate type MOSTFTs described above. This active matrixLCD has a flat panel configuration in which the main substrate 61 (thisforms an active matrix substrate) is bonded to the counter substrate 98with spacers (not shown) therebetween, and between both substrates 61and 98, liquid crystal (not shown in this figure) is enclosed. On thesurface of the main substrate 61, there are provided display portioncomposed of pixel electrodes 93 disposed in a matrix and switchingelements driving these pixel electrodes and the peripheral drivingcircuit portion connected to this display portion.

[0495] The switching element in the display portion is formed of one ofthe n-type MOS, p-type MOS, and CMOS described above, these devicesbeing a top gate type MOSTFT having an LDD structure. In addition, inthe peripheral driving circuit portion, as circuit elements, one of theCMOS, n-type MOS, and p-type MOSTFT having a top gate type MOSTFT may beused, or the combination thereof may also be used. One of the peripheraldriving circuit portions is a horizontal driving circuit which suppliesa data signal and drives MOSTFTs of individual pixels on each horizontalline, the other peripheral driving circuit portion is a vertical drivingcircuit which drives gates of MOSTFTs of individual pixels on eachscanning line, and these circuit portions are generally provided at twosides of the display portion. These driving circuits may be adot-sequential analog system or a line-sequential digital system.

[0496] As shown in FIG. 38, the MOSTFTs are disposed at theintersections of gate bus lines and data bus lines, which intersect eachother at right angles, so that image information is written in a liquidcrystal capacity (C_(LC)) via the MOSTFT, and the charge is retaineduntil next information is input. In this case, since only the channelresistance of TFT is insufficient for retaining the information, inorder to compensate for the insufficient channel resistance, a storagecapacity (auxiliary capacity) (C_(s)) may be added in parallel with theliquid crystal capacity for suppressing a decrease in the liquid crystalvoltage due to a leakage current. Of the MOSTFTs for forming an LCD,characteristics required for TFTs used in the display portion differfrom those of TFTs used in the peripheral driving circuit portion, andin particular, for the MOSTFTs in the pixel portion, it is important tocontrol an Off current and to ensure an On current. Accordingly, byforming the MOSTFTs each having an LDD structure in the display portionso that an electric field is not easily applied across the gate anddrain, an effective electric field applied to the channel region can bedecreased, an off current can be decreased, and the change in propertiescan also be decreased. However, since problems may arise in that theprocess therefor becomes complicated, the element size is alsoincreased, and the On current is decreased, an optimum designing must beperformed in accordance with individual applications.

[0497] As liquid crystal which may be used, in addition to TN liquidcrystal (nematic liquid crystal used in a TN mode of active matrixdrive), STN (super-twisted nematic), GH (guest-host), PC (phase change),FLC (ferroelectric liquid crystal), AFLC (antiferroelectric liquidcrystal), PDLC (polymer dispersion-type liquid crystal), and the likemay be used.

[0498] <LCD Manufacturing Example 2>

[0499] Next, a manufacturing example of an LCD (liquid crystal displaydevice) using a polycrystalline silicon MOSTFT, formed by a lowtemperature process, of this embodiment will be described (thismanufacturing example may be applied to display regions or the like ofan organic EL or an FED, which will be described later).

[0500] In this embodiment, a low strain point glass, such asaluminosilicate glass or borosilicate glass, or a heat resistant resinsuch as polyimide is used as the substrate 61, and the steps shown inFIGS. 34(1) and (2) are performed in a manner similar to that in themanufacturing example 1 described above. That is, the polycrystallinesilicon thin-film 67 which may (or may not) contain tin is formed on thesubstrate 61 by catalytic CVD and flash lamp annealing and are thenprocessed so that islands are formed thereon, and subsequently, n-typeMOSTFT portions in the display region, and n-type MOSTFT portions andp-type MOSTFT portions in the peripheral driving circuit region areformed. In this case, at the same time, regions of diodes, capacitors,inductances, resistors, and the like are formed. As is the casedescribed above, the process performed hereinafter will be describedabout MOSTFT; however, it is naturally understood that the process bethe same as that for forming the other elements.

[0501] Next, as shown in FIG. 39(1), in order to optimize the V_(th) bycontrolling dopant concentrations in gate channel regions of theindividual MOSTFTs, the n-type MOSTFT portion in the display region andthe n-type MOSTFT portion in the peripheral driving circuit region arecovered with the photoresist 82, and the n-type dopant 79, such asphosphorus or arsenic, is then doped in the p-type MOSTFT portion in theperipheral driving circuit region at a dose rate of 1×10¹² atoms/cm² byion implantation or ion doping so as to have a donor concentration of2×10¹⁷ atoms/cc. In addition, as shown in FIG. 39(2), the p-type MOSTFTportion in the peripheral driving circuit region is covered with thephotoresist 82, and the p-type dopant 83 such as boron is then doped inthe n-type MOSTFT portion in the display region and the n-type MOSTFTportion in the peripheral driving circuit region at a dose rate of5×10¹¹ atoms/cm² by ion implantation or ion doping so as to have anacceptor concentration of 1×10¹⁷ atoms/cc.

[0502] Next, as shown in FIG. 39(3), in order to form n⁻-type LDD(Lightly Doped Drain) of the n-type MOSTFT in the display region forimproving switching properties, by common photolithographic technique,the gate portion of the n-type MOSTFT in the display region and theentire p-type MOSTFT and the n-type MOSTFT in the peripheral drivingcircuit region are covered with the photoresist 82, and in the exposedsource and drain regions of the n-type MOSTFT in the display region, then-type dopant 79 such as phosphorus is dopes at a dose rate of 1×10¹³atoms/cm² by ion implantation or ion doping so as to have a donorconcentration of 2×10¹⁸ atoms/cc, thereby forming the n⁻-type LDDportions.

[0503] Next, as shown in FIG. 40(4), the entire n-type MOSTFT portion inthe display region and the gate portion of the p-type MOSTFT portion inthe peripheral driving circuit region are covered with the photoresist82, and in the exposed source and drain regions, the p-type dopant 83such as boron is dopes at a dose rate of 1×10¹⁵ atoms/cm² by ionimplantation or ion doping so as to have an acceptor concentration of2×10²⁰ atoms/cc, thereby forming p⁺-type source portion 84 and drainportion 85.

[0504] Next, as shown in FIG. 40(5), the p-type MOSTFT portion in theperipheral driving circuit region is covered with the photoresist 82,the gate and the LDD portions of the n-type MOSTFT in the display regionand the gate portion of the n-type MOSTFT portion in the peripheraldriving circuit region are covered with the photoresist 82, and in theexposed source and drain regions of the n-type MOSTFTs in the displayregion and in the peripheral driving region, the n-type dopant 79 suchas phosphorus or arsenic is dopes at a dose rate of 1×10¹⁵ atoms/cm² byion implantation or ion doping so as to have a donor concentration of2×10²⁰ atoms/cc, thereby forming n⁺-type source portions 80 and drainportions 81.

[0505] Next, as shown in FIG. 40(6), by plasma CVD, reduced-pressureCVD, catalytic CVD, or the like, as the gate insulating film 68, alaminated film composed of a silicon oxide film (40 to 50 nm thick), asilicon nitride film (10 to 20 nm thick), and a silicon oxide film (40to 50 nm thick) is formed. Subsequently, RTA treatment is performed at,for example, approximately 1,000° C. for 10 to 20 seconds using halogenlamps or the like so as to activate the n-type and the p-type dopants,thereby obtaining individual dopant concentrations determinedbeforehand.

[0506] Next, an aluminum film containing 1% Si is formed by sputteringover the entire surface to have a thickness of 400 to 500 nm and is thenformed into the gate electrodes 75 and gate lines of all MOSTFTs bycommon photolithographic and etching techniques. Furthermore, by plasmaCVD, catalytic CVD, or the like, the insulating film 86, which is alaminate, composed of a silicon-oxide film (100 to 200 nm thick), and aphosphine silicate glass film (PSG) film (200 to 300 nm thick) isformed.

[0507] Subsequently, by common photolithographic and etching technique,widow holes are formed in the source and the drain portions of allMOSTFTs of the peripheral driving circuit and in the source portions ofthe display n-type MOSTFTs. The silicon nitride film is processed byplasma etching using CF₄, and the silicon oxide film and the phosphinesilicate glass film are etched using a fluorinated etching solution.

[0508] Next, as shown in FIG. 40(7), an aluminum film containing 1% Siis formed by sputtering over the entire surface to have a thickness of400 to 500 nm and is then formed into the source and the drainelectrodes 88, 89, 90, and 91 of all MOSTFTs in the peripheral drivingcircuit by common photolithographic and etching techniques, andsimultaneously, the source electrodes 87 of the display n-type MOSTFTand data lines are formed.

[0509] Next, although no shown in the figure, by plasma CVD,reduced-pressure CVD, catalytic CVD, or the like, a silicon oxide film(100 to 200 nm thick), a phosphine silicate glass film (200 to 300 nmthick), and a silicon nitride film (100 to 300 nm thick) are formed overthe entire surface, and hydrogenating and sintering treatment is thenperformed in a forming gas at approximately 400° C. for 1 hour.Subsequently, windows are formed at the drain portions of the displayn-type MOSTFTS.

[0510] In the step described above, when a silicon nitride film (500 to600 nm) for passivation, containing a large amount of hydrogen, isformed by plasma CVD for forming the laminate structure, byhydrogenating treatment at 420° C. for approximately 30 minutes in anitrogen or a forming gas, the carrier mobility can be improved due toimprovement in interface properties by hydrogen diffusion in the siliconnitride film for passivation and improvement in crystallinity atdangling bonds of the polycrystalline silicon thin-film. In this step,since a silicon nitride film tends to trap hydrogen therein, in order toimprove the effect of hydrogenating treatment, the structure in which apolycrystalline silicon thin-film is sandwiched between silicon nitridefilms, as in this embodiment, that is, a laminate formed of a glasssubstrate, a protective silicon nitride film for blocking Na ions+asilicon oxide film, a polycrystalline silicon thin-film, a gateinsulating film (a silicon oxide film or the like), a gate electrode, asilicon oxide film, and a silicon nitride film for passivation, ispreferably use (this structure is also preferable in other examples). Inthis case, by hydrogenating treatment, silicon sintering treatment ofthe aluminum alloy films containing 1% Si and silicon in the source anddrain regions are simultaneously performed, thereby obtaining ohmiccontacts.

[0511] When the LCD is a transmissive type, the silicon oxide film, thephosphine silicate glass film, and the silicon nitride film in the pixelaperture portions are removed, and when the LCD is a reflective type, itis not necessary to remove the silicon oxide film, the phosphinesilicate glass film, and the silicon nitride film in the pixel apertureportions (these are applied to the LCDs described above or below).

[0512] In the case of transmissive type, as is the case shown in FIG.36(10), after an acrylic transparent resin planarizing film 2 to 3 μmthick is formed over the entire surface by spin coating or the like, andwindows are formed in the transparent resin at the drain side of thedisplay MOSTFTs by common photolithographic and etching techniques, anITO sputtering film 130 to 150 nm thick is formed over the entiresurface, and ITO transparent electrodes connected to the drain portionsof the display MOSTFTs are formed by common photolithographic andetching techniques. In addition, heat treatment (200 to 250° C. for 1hour in a forming gas) is performed so that the contact resistance isdecreased, and that the ITO transparency is improved.

[0513] In the case of reflective type, after a photosensitive resin film2 to 3 μm thick is formed over the entire surface by spin coating or thelike, by common photolithographic and etching techniques, an irregularpattern is formed at least in the pixel portions, and an irregularunderlying portion is formed by reflow. Simultaneously, windows areformed in the photoresist resin film at the drain portions of thedisplay n-type MOSTFTS. Subsequently, an aluminum sputtering film 300 to400 nm thick containing 1% Si is formed over the entire surface, and bycommon photolithographic and etching techniques, the entire aluminumfilm other than that provided on the pixel portions is removed, therebyforming an aluminum reflecting portions having irregular shape connectedto the drain electrodes of the display n-type MOSTFTS. Subsequently,sintering treatment is performed at 300° C. for 1 hour in a forming gas.

[0514] In the case described above, when flash lamp annealing isperformed after the sources and the drains of the MOSTFTs are formed,the film temperature of the low-crystallization silicon thin-film islocally increased, the crystallization is facilitated, and hence, a highquality polycrystalline silicon thin-film having high mobility can beformed. At the same time, since phosphorus, arsenic, boron ions, or thelike doped in the gate channel, source, and drain regions are activated,and hence, the productivity may be improved in some cases.

[0515] <Bottom Gate Type or Dual Gate Type MOSTFT>

[0516] In LCDs or the like incorporating MOSTFTs, instead of the topgate type described above, an example of manufacturing a transmissivetype LCD using bottom gate type and dual gate type MOSTFTs will bedescribed (however, a reflective type LCD can also be manufactured bythe same method as described below).

[0517] As shown in FIG. 41(B), bottom gate type MOSTFTs are provided inthe display portion and in the peripheral portion, or as shown in FIG.41(C), in the display portion and in the peripheral portion, dual gatetype MOSTFTs are provided. Of these bottom gate and the dual gateMOSTFTs, in particular, in the case of the dual gate type, since thedriving capability can be improved by the top and the bottom gates, thedual gate type is suitably used for a high-speed switching and ahigh-current driving large panel and, in addition, may be operated as atop gate type or a bottom gate type by selectively using one of the topand the bottom gates.

[0518] In a bottom gate type MOSTFT shown in FIG. 41(B), referencenumeral 102 in the figure indicates a gate electrode composed of heatresistant Mo or Mo—Ta alloy, reference numeral 103 indicates a siliconnitride film, reference numeral 104 indicates a silicon oxide film,these two films forming a bottom gate insulating film, and on this gateinsulating film, a channel region or the like using the polycrystallinesilicon thin-film 67 equivalent to that used for the top gate typeMOSTFT is formed. In addition, in the dual gate type MOSTFT shown inFIG. 41(C), the bottom gate portion thereof is equivalent to that of thebottom gate type MOSTFT; however, in the top gate portion, a gateinsulating film 106 is formed of a silicon oxide film, a laminatecomposed of silicon oxide and silicon nitride, or a laminate of siliconoxide, silicon nitride, and silicon oxide film, and on this insulatingfilm, the top gate electrode 75 is formed.

[0519] <Manufacturing of Bottom Gate Type MOSTFT>

[0520] First, a sputtering film of heat resistant Mo or an Mo—Ta alloyhaving a thickness of 300 to 400 nm is formed on the entire surface ofthe glass substrate 61 and is then processed by taper etching at anangle of 20 to 45° by common photolithographic and etching techniques soas to form bottom gate electrodes 102 at least in the TFT formingregions, and at the same time, gate lines are also formed. The selectionof a glass material may be performed in accordance with the case of thetop gate type described above.

[0521] Next, by vapor-phase growth, such as plasma CVD, catalytic CVD,or reduced-pressure CVD, the silicon nitride film 103 and the siliconoxide film 104, which are used as a protective, gate insulating film,and the microcrystalline silicon thin-film 67A, which may or may notcontain tin and contains amorphous silicon, are formed. In addition,this film is formed into the polycrystalline silicon thin-film 67 whichmay or may not contain tin by performing flash lamp annealing, as in thecase described above. These vapor-phase film forming conditions areequivalent to those for the top gate type described above. In addition,the silicon nitride film used as the bottom gate insulating film and theprotection film is formed so as to stop sodium ions from the glasssubstrate; however, when synthetic quartz glass is used, the siliconnitride film is not necessary. As is the case described above, thereflection-reflecting, protective film (a silicon oxide film or thelike) may be formed on the low-crystallization silicon thin-film 67A andmay be processed by flash lamp annealing. In addition, after islands areformed for MOSTFT forming regions or the like, flash lamp annealing maybe performed.

[0522] Subsequently, as is the case described above, in order tooptimize the V_(th) by controlling the dopant concentrations inindividual channel regions after islands (however, one of the regions isonly shown in the figure: hereafter, the same as above) are formed forthe p-type MOSTFT and the n-type MOSTFT regions by commonphotolithographic and etching techniques, an appropriate amount of ann-type or a p-type dopant is doped by ion implantation or ion doping,and furthermore, in order to form the source and the drain regions ofthe individual MOSTFTs, an appropriate amount of an n-type or a p-typedopant is doped by ion implantation or ion doping. Subsequently,annealing is performed by RTA or the like for activating these dopants.

[0523] The process performed hereinafter is equivalent to that describedabove.

[0524] <Manufacturing of Dual Gate Type MOSTFT>

[0525] As is the bottom gate type described above, the bottom gateelectrodes 102, bottom gate lines, the bottom gate insulating films 103and 104, the polycrystalline silicon thin-film 67 which may or may notcontain tin are formed. The silicon nitride film 103 used as the bottomgate insulating film and the protection film is formed so as to servestopping sodium ions from the glass substrate; however, when syntheticquartz glass is used, the silicon nitride film is not necessary. As isthe case described above, the reflection-reflecting, protective film (asilicon oxide film or the like) may be formed on the low-crystallizationsilicon thin-film 67A and may be processed by flash lamp annealing. Inaddition, after islands are formed for the MOSTFT forming regions or thelike, flash lamp annealing may be performed.

[0526] Subsequently, as in the case described above, after islands areformed for the p-type MOSTFT and the n-type MOSTFT regions by commonphotolithographic and etching techniques, in order to optimize theV_(th) by controlling the dopant concentrations in individual channelregions, an appropriate amount of an n-type or a p-type dopant is dopedby ion implantation or ion doping, and furthermore, in order to form thesource and the drain regions of the individual MOSTFTs, an appropriateamount of an n-type or a p-type dopant is doped by ion implantation orion doping. Subsequently, annealing is performed by RTA or the like foractivating these dopants.

[0527] Next, a silicon oxide film, a laminate of silicon oxide film anda silicon nitride film, or a laminate of silicon oxide film, a siliconnitride film, and a silicon oxide film is formed as the top gateinsulating film 106. The vapor-phase deposition conditions areequivalent to those for the top gate type.

[0528] Next, an aluminum film containing 1% Si is formed by sputteringover the entire surface to have a thickness of 400 to 500 nm and is thenformed into the top gate electrodes 75 and top gate lines of all MOSTFTsby common photolithographic and etching techniques. Subsequently, byplasma CVD, catalytic CVD, or the like, a silicon oxide film (100 to 200nm thick), a phosphine silicate glass (PSG) film (200 to 300 nm thick),and a silicon nitride film (100 to 300 nm thick) are deposited so as toform the multilayer insulating film 86. Subsequently, windows are formedat the source and the drain electrode portions of all MOSTFTs in theperipheral driving circuit and at the source electrode portions of thedisplay n-type MOSTFTs.

[0529] Next, an aluminum film containing 1% Si is formed by sputteringover the entire surface to have a thickness of 400 to 500 nm, and bycommon photolithographic and etching techniques, the aluminum electrodes87 and 88 of the sources and drains of all MOSTFTS in the peripheraldriving circuit and the aluminum electrodes 89, source lines, and wiresof the display n-type MOSTFTs are formed. Subsequently, sinteringtreatment is performed at approximately 400° C. for 1 hour in a forminggas. Next, as in the case described above, after an insulating film isformed over the entire surface, transparent pixel electrodes composed ofITO film or the like connected to the drain electrode portions of thedisplay n-type MOSTFTs are formed.

[0530] As described above, according to this embodiment, as in the firstembodiment described above, by a vapor-phase growth such as catalyticCVD or plasma CVD and flash lamp annealing, the polycrystalline siliconthin-film can be formed, in which the carrier mobility is high, thecontrol of the V_(th) is easily performed, and high speed operation canbe performed at low resistance. In addition, the gate channel, source,and drain regions of the MOSTFTs of the display portion and theperipheral driving circuit portion of the LCD are formed of thispolycrystalline silicon thin-film. According to the top gate type,bottom gate type, and the dual gate type liquid crystal devices usingthis polycrystalline silicon thin-film, the configuration in which adisplay portion provided with an LDD structure having superior switchingproperties and low leakage current is integrated with peripheralcircuits, such as high-performance driving circuits, image signalprocessing circuits, memory circuits or the like can be realized, and asa result, an inexpensive liquid crystal panel having high image quality,highly fine display, narrow picture frame, and high efficiency can berealized.

[0531] In addition, since formation can be performed at a lowtemperature (300 to 400° C.), a low strain point glass or a heatresistant resin substrate, which is inexpensive and is easily formedinto large substrates, can be used, and hence, cost reduction can berealized. In addition, by forming color filters and a black mask on thearray portions, the aperture ratio, illuminance, and the like of theliquid crystal panel are improved, no color filter substrate isrequired, and cost reduction can be realized due to improvement inproductivity.

[0532] <LCD Manufacturing Example 3>

[0533] FIGS. 42 to 44 include views showing another manufacturingexample of an active matrix LCD.

[0534] First, as shown in FIG. 42(1), at least in the TFT formingregions on one major surface of the insulating substrate 61 composed ofborosilicate glass, aluminosilicate glass, quartz glass, transparentcrystallized glass, or the like, a photoresist having a predeterminedpattern is formed. Subsequently, by using common photolithographic andetching techniques such as reactive ion etching (RIE), the substrate isirradiated with F⁺ ions formed by CF₄ plasma using the photoresist as amask, and as a result, a plurality of recess portions, which is providedwith a step 223 and has an appropriate shape and dimensions, are formedin the substrate 61.

[0535] The step 223 is a seed used for graphoepitaxial growth of singlecrystalline silicon described below. The step may have a depth d of 0.01to 0.03 μm, a width w of 1 to 5 μm, and a length of (directionperpendicular to the plane) 5 to 10 μm, and the angle (base angle) ofthe step, which is formed by the bottom surface and the side surfacethereof, is a right angel. In addition, in order to prevent diffusion ofNa ions or the like from the glass substrate, a silicon nitride film (50to 200 nm thick) and a silicon oxide film (300 to 400 nm thick) arecontinuously formed beforehand on the surface of the substrate 1, andthe plurality of recess portions, which are provided with steps andwhich have an appropriate shape and dimensions, may be formed in thissilicon oxide film.

[0536] Next, as shown in FIG. 42(2), after the photoresist is removed,the low-crystallization silicon thin-film 67A having a thickness of 50nm, which may or may no contain a Group IV element such as tin, isformed over the entire one major surface of the insulating substrate 61including the steps 223.

[0537] Next, as shown in FIG. 43(3), while the low-crystallizationsilicon thin-film 67A is placed in a fusion state by flash emission 221performed for flash lamp annealing and is then slowly cooled, singlecrystalline silicon thin-film 67 is grown in accordance withgraphoepitaxial growth from the corners of the bottom surface of thesteps 223, which are used as a seed, not only in the recesses but alsoon the peripheral portions thereof in the lateral direction. In theabove step, as in the case described above, after thelow-crystallization silicon thin-film is covered with areflection-reducing, protective, insulating film and is furtherprocessed so that islands are formed thereon, this flash lamp annealingmay be performed. By repeating this flash lamp annealing and formationof the low-crystallization semiconductor thin-film so as to form alaminate, a single crystalline semiconductor thick film having athickness in the order of micrometers may be formed (hereafter, the sameas described above).

[0538] As described above, for example, the (100) plane of the singlecrystalline silicon thin-film 67 is grown on the substrate in accordancewith graphoepitaxial growth. In this case, the step 223 serves as a seedfor epitaxial growth, which is called graphoepitaxial growth, by highenergy of flash lamp annealing and facilitates the growth, therebyforming the single crystalline silicon thin-film 67 (approximately 50 nmthick) having higher crystallinity. Related to this, as shown in FIG.43, when a vertical wall similar to the above step 223 is formed on theamorphous substrate (glass) 61, and an epitaxy layer is formed thereon,although crystals having random plane directions as shown in FIG. 43(a)are grown as shown in FIG. 43(b), that is, the (100) plane thereof isepitaxially grown along the surface of the step 223. In addition, bychanging the shape of step described above as shown in FIGS. 44(a) to(f), the plane orientation of grown layers can be controlled. When MOStransistors are formed, the (100) plane is mostly used. That is,concerning the cross-sectional shape of the step 223, the angle (baseangle) at the corner of the bottom surface may be a right angle or maybe inclined inwardly or outwardly from the top edge to the bottom edge,and after all, the step may have a specific plane direction so that thecrystal is easily grown. It is preferably that the base angle of thestep 223 be 90° or less in general, and that the corner portions of thebottom surface have a slight curvature.

[0539] As described above, after the single crystalline siliconthin-film 67 is formed on the substrate 61 by graphoepitaxial growth inflash lamp annealing, a top gate type MOSTFT in which the singlecrystalline silicon thin-film 67 (approximately 50 nm thick) is used asan active layer is formed in a manner equivalent to that describedabove.

[0540] In addition, after a heat resistant resin substrate such aspolyimide is used as the substrate 61, recesses which are provided withsteps 223 having a predetermined size and dimensions are formed at leastin the TFT forming regions on the substrate, the same process asdescribed above may be performed. For example, a mold provided withprotrusions having predetermined dimensions and a shape, for example,0.03 to 0.05 μm high, 5 μm wide, and 10 μm long is stamped on apolyimide substrate 100 μm thick, thereby forming recesses having thedimensions and shape approximately equivalent to those of the mold.Alternatively, a heat resistant resin film (5 to 10 μm thick) such aspolyimide is formed on a metal plate such as stainless steel used as areinforcing material by coating, screen printing, or the like, and amold provided with protrusions having predetermined dimensions and ashape, for example, 0.03 to 0.05 μm high, 5 μm wide, and 10 μm long, isstamped on the resin film described above, thereby forming recesseshaving the dimensions and shape approximately equivalent to those of themold. Hereinafter, the formation of the single crystalline siliconthin-film and the formation of the MOSTFTs are performed by the stepssimilar to those described above.

[0541] As described above, according to this embodiment, by forming therecesses provided with the steps 223 having a predetermined shape anddimensions in the substrate 61, and by performing graphoepitaxial growthby flash lamp annealing using the recesses as a seed, the singlecrystalline silicon thin-film 67 having high carrier mobility can beobtained, and hence, an LCD incorporating a high performance drivertherein can be manufactured.

[0542] <LCD Manufacturing Example 4>

[0543]FIG. 45 includes views showing still another manufacturing exampleof an active matrix LCD.

[0544] First, as shown in FIG. 45(1), at least in the FTF formingregions on one major surface of an insulating substrate 61, acrystalline sapphire thin-film (a thickness of 10 to 200 nm) 224 havinggood lattice matching properties with single crystalline silicon isformed. By high density plasma CVD, catalytic CVD, or the like, thiscrystalline sapphire thin-film 224 is formed by oxidizing trimethylaluminum with an oxidizing gas (oxygen, moisture, ozone, or the like)followed by crystallization. As the insulating substrate 61, a high heatresistant glass substrate formed of quartz glass or the like, a lowstrain point glass substrate formed of borosilicate glass,aluminosilicate glass, or the like, a heat resistant resin substrateformed of polyimide or the like, or the like may be used.

[0545] Next, as shown in FIG. 45(2), by catalytic CVD, plasma CVD, orthe like, a low-crystallization silicon thin-film 67A having a thicknessof, for example, 50 nm is formed on the crystalline sapphire thin-film224.

[0546] Next, as shown in FIG. 45(3), while the low-crystallizationsilicon thin-film 67A is placed in a fusion state by flash emission 221performed in flash lamp annealing and is then slowly cooled, singlecrystalline silicon thin-film 67 is grown in accordance withheteroepitaxial growth using the crystalline sapphire thin-film 224 as aseed. In the above step, as in the case described above, after thelow-crystallization silicon thin-film is covered with areflection-reducing, protective, insulating film and is furtherprocessed so that islands are formed thereon, this flash lamp annealingmay be performed. That is, since the crystalline sapphire thin-film 224has good lattice matching properties with single crystalline silicon, aspecific plane, such as the (100) plane, of the single crystallinesilicon is effectively grown on the substrate in accordance withheteroepitaxial growth by using the sapphire thin-film 224 as a seed. Inthe case described above, when the step 223 described above is formed,and the crystalline sapphire thin-film 224 is grown on a surfaceincluding the step 223, by heteroepitaxial growth in cooperation withgraphoepitaxial growth starting from the step 223, the singlecrystalline silicon thin-film 67 having higher crystallinity can beobtained. In addition, by repeating flash lamp annealing and formationof a low-crystallization semiconductor thin-film so as to form alaminate, a single crystalline semiconductor thick film having athickness in the order of micrometers may be formed.

[0547] As described above, after the single crystalline siliconthin-film 67 is formed on the substrate 61 by heteroepitaxial growth inflash lamp annealing, a top gate type MOSTFT in which the singlecrystalline silicon thin-film 67 (approximately 50 nm thick) is used asan active layer is formed in a manner equivalent to that describedabove.

[0548] As described above, according to this embodiment, by performingheteroepitaxial growth by flash lamp annealing using the crystallinesapphire thin-film 224 provided on the substrate 61 as a seed, thesingle crystalline silicon thin-film 67 having high carrier mobility canbe obtained, and hence, an LCD incorporating a high performance drivertherein can be manufactured.

[0549] In addition, since the above-mentioned material layer, such asthe crystalline sapphire thin-film 224, serves as a barrier againstdiffusion of various atoms, the diffusion of impurities from the glasssubstrate 61 can be prevented. Since this crystalline sapphire thin-filmhas a sodium ion stopping effect, when the thickness thereof issufficiently large, at least a silicon nitride film among the underlyingprotection films can be omitted.

[0550] Instead of the crystalline sapphire thin-film, a material layer,having a function substantially equivalent thereto, formed of at leastone selected from the group consisting of a spinel material, calciumfluoride, strontium fluoride, barium fluoride, boron phosphide, yttriumoxide, and zirconium oxide may be formed.

[0551] Third Embodiment

[0552] In this embodiment, the present invention is applied to anorganic or an inorganic electroluminescent (EL) display devices, such asan organic EL display device. Hereinafter, the structural examples andthe manufacturing examples will be described. In this embodiment, a topgate type MOSTFT will be described, and it is naturally understood thatthe present invention be applied to a bottom gate type or a dual gatetype MOSTFT.

[0553] <Structural Example I of Organic EL Element>

[0554] As shown in FIGS. 46(A) and (B), according to this structuralexample I, by using a polycrystalline silicon thin-film (or a singlecrystalline silicon thin-film: hereinafter, the polycrystalline siliconthin-film will be described by way of example; however, the samedescription thereof can also be applied to the single crystallinesilicon thin-film), which may or may not contain tin and which has alarge grain size and high crystallinity, formed on a substrate 111composed of glass or the like by the method described above according tothe present invention, gate channel regions 117, source regions 120, anddrain regions 121 of a switching MOSTFT 1 and a current driving MOSTFT 2are formed. In addition, gate electrodes 115 are formed on the gateinsulating film 118, on the source and the drain regions, the sourceelectrodes 127 and the drain electrodes 128 and 131 are formed. Thedrain of the MOSTFT 1 is connected to the gate of the MOSTFT 2 via thedrain electrode 128, capacitor C is formed between drain of the MOSTFT 1and the source electrode 127 of the MOSTFT 2 with an insulating film 136therebetween, and the drain electrode 131 of the MOSTFT 2 extends to acathode 138 of an organic EL element. In this case, an LDD portion maybe formed in the switching MOSTFT 1 so as to improve the switchingproperties.

[0555] The individual MOSTFTs are covered with an insulating film 130,on this insulating film, for example, a green organic light-emittinglayer 132 (or a blue organic light-emitting layer 133, or a red organiclight-emitting layer, not shown in the figure) of the organic EL elementis formed so as to cover the cathode, an anode (first layer) 134 isformed so as to cover this organic light-emitting layer, and inaddition, a common anode (second layer) 135 is further formed over theentire surface. In this embodiment, a method for manufacturing aperipheral driving circuit, an image signal processing circuit, a memorycircuit, or the like formed of CMOSTFTs is performed in a mannerequivalent to that for the liquid crystal display device described above(hereafter, the same as described above).

[0556] In the organic EL display portion of this structure, the organicEL light-emitting layer is connected to the drain of the current drivingMOSTFT 2, the cathode (Li—Al, Mg—Ag, or the like) 138 is provided on thesurface of the substrate 111 compose of glass or the like, and theanodes (ITO film or the like) 134 and 135 are provided thereon, so thatan upper surface emission 136 type is formed. In addition, when thecathode covers the MOSTFTs, the light emission area is increased, andthe cathode serves as a shading film in this case so that emission lightdoes not enter the MOSTFTS, degradation of TFT properties does notoccur.

[0557] In addition, as show in FIG. 46(C), when a black mask portion(chromium, chromium dioxide, or the like) 140 is formed around theperiphery of each pixel portion, light leakage (crosstalk or the like)can be prevented, and the contrast can be improved.

[0558] In addition, by a method for using three color light-emittinglayers, that is, green, blue, and red, in the pixel display portions, amethod for using color conversion layers, and a method for using a colorfilter for a white light-emitting layer, superior full color organic ELdisplay device can be realized. In addition, by a spin coating methodfor polymer materials used as individual light-emitting materials orvacuum heating deposition of a metal complex, full color organic ELportions having longer life, high accuracy, high quality, and highreliability can be formed at a good productivity rate, and hence, costreduction can be realized (hereafter, the same as described above).

[0559] Next, a process for manufacturing this organic EL element will bedescribed. First, as shown in FIG. 47(1), after the source regions 120,the channel regions 117, and the drain regions 121 are formed from thepolycrystalline silicon thin-film by the steps described above, the gateinsulating film 118 is formed, the gate electrodes 115 of the MOSTFTs 1and 2 are formed on the insulating film 118 by sputtering of a Mo—Taalloy or the like and by common photolithographic and etchingtechniques, and at the same time, a gate line connected to the gateelectrode of the MOSTFT 1 is formed. Next, after an overcoat film (asilicon oxide film or the like) 137 is formed by vapor-phase growth suchas catalytic CVD (hereafter, the same as above), the source electrode127 and an earth line of the MOSTFT 2 are formed by sputtering of aMo—Ta alloy or the like and by common photolithographic and etchingtechniques, and in addition, an overcoat film (a laminate of siliconoxide and silicon nitride) 136 is formed. By RTA (Rapid Thermal Anneal)treatment (for example, approximately 1,000° C. for 30 seconds) using ahalogen lamp or the like, an n-type or a p-type dopant, which has beenion-doped, is activated.

[0560] Next, as shown in FIG. 47(2), after windows are provided at thesource and the drain portions of the MOSTFT 1 and the gate portion ofthe MOSTFT 2, as shown in FIG. 47(3), by a sputtering film-formingtechnique using Al containing 1% Si and by common photolithographic andetching techniques, the drain electrode of the MOSTFT 1 and the gateelectrode of the MOSTFT 2 are connected to each other by an Al wire 128containing 1% Si, and at the same time, the source electrode of theMOSTFT 1 and a source line, which is formed of Al containing 1% Si andis connected to this electrode, are formed. Next, an overcoat film (alaminated film of silicon oxide, phosphine silicate glass, and siliconnitride, or the like) 130 is formed, a window is formed at the drainportion of the MOSTFT 2, and the cathode 138 in the light-emittingportion connected to the drain proton of the MOSTFT 2 is formed. Next,hydrogenating and sintering treatment is performed.

[0561] Next, as shown in FIG. 47(4), the organic light-emitting layer132 or the like and the anodes 134 and 135 are formed.

[0562] In the element shown in FIG. 46(B), instead of the (Rapid ThermalTreatment) organic light-emitting layer, a known light-emitting polymeris used, a active matrix drive light-emitting polymer display device(LEPD) can be formed (hereafter, the same as described above).

[0563] <Structural Example II of Organic EL Element>

[0564] As shown in FIGS. 48(A), (B), according to this structuralexample II, as is the structural example I described above, by using thepolycrystalline silicon thin-film, which may or may not contain tin andwhich has a large grain size and high crystallinity, formed on thesubstrate 111 composed of glass or the like by the method describedabove according to the present invention, the gate channels 117, thesource regions 120, and the drain regions 121 of the switching MOSTFT 1and the current driving MOSTFT 2 are formed. In addition, the gateelectrodes 115 are formed on the gate insulating film 118, on the sourceand the drain regions, the source electrodes 127 and the drainelectrodes 128 and 131 are formed. The drain of the MOSTFT 1 isconnected to the gate of the MOSTFT 2 via the drain electrode 128, thecapacitor C is formed between drain of the MOSTFT 1 and the drainelectrode 131 with the insulating film 136 therebetween, and the sourceelectrode 127 of the MOSTFT 2 extends to an anode 144 of the organic ELelement. In this case, an LDD portion may be formed in the switchingMOSTFT 1 so as to improve the switching properties.

[0565] The individual MOSTFTs are covered with the insulating film 130,on this insulating film, for example, the green organic light-emittinglayer 132 (or the blue organic light-emitting layer 133, or a redorganic light-emitting layer, not shown in the figure) of the organic ELelement is formed so as to cover the anode, a cathode (first layer) 141is formed so as to cover this organic light-emitting layer, and inaddition, a common cathode (second layer) 142 is further formed over theentire surface.

[0566] In the organic EL display portion of this structure, the organicEL light-emitting layer is connected to the source of the currentdriving MOSTFT 2 and is formed so as to cover the anode 144 provided onthe surface of the substrate 111 composed of glass or the like, thecathode 141 is formed so as to cover the organic EL light-emittinglayer, and the cathode 142 is formed over the entire surface, so that abottom surface emission 136 type is formed. In addition, the cathode isprovided between the organic EL light-emitting layers and over theMOSTFTS. That is, for example, after the green organic light-emitting ELlayer is formed by vacuum heating deposition or the like, and the greenorganic light-emitting EL portion is formed by a photolithographic and adry etching method, the blue and the red organic light-emitting ELportions are continuously formed in a manner as described above, and thecathode (electron injection layer) 141 is finally formed on theindividual portions from a magnesium-silver alloy or an aluminum-lithiumalloy. Since this entire surface is tightly sealed with the cathode(electron injection layer) 142, the intrusion of moisture between theorganic EL layers from the outside is prevented particularly by thecathode 142 covering the entire surface, and degradation of the organicEL layers having poor resistance against moisture and oxidation of theelectrodes are prevented, so that a longer life, higher quality, andhigh reliability can be achieved (since the entire surface is coveredwith the anode in the structural example I shown in FIG. 46, the sameadvantages described above can also be obtained). In addition, since theheat dissipation effect is improved by the cathodes 141 and 142, thechange in structure (fusion or recrystallization) of the organic ELthin-film caused by heat generation is reduced, so that a longer life,higher quality, and high reliability can be achieved. Furthermore,accordingly, full color organic EL layer having high accuracy and highquality can be manufactured at a good productivity rate, and hence, costreduction can be realized.

[0567] In addition, as show in FIG. 48(C), when the black mask portion(chromium, chromium dioxide, or the like) 140 is formed around theperiphery of each pixel portion, light leakage (crosstalk or the like)can be prevented, and the contrast can be improved. This black maskportion 140 is covered with an insulating film, for example, a siliconoxide film 143 (this may be simultaneously formed when the gateinsulating film 118 is formed and may also be formed of the same layeras that therefor).

[0568] Next, a process for manufacturing this organic EL element will bedescribed. First, as shown in FIG. 49(1), after the source regions 120,the channel regions 117, and the drain regions 121 are formed from thepolycrystalline silicon thin-film by the steps described above, the gateinsulating film 118 is formed by vapor-phase growth such as catalyticCVD, the gate electrodes 115 of the MOSTFTs 1 and 2 are formed on thisinsulating film 118 by sputtering of a Mo—Ta alloy or the like and bycommon photolithographic and etching techniques, and at the same time, agate line connected to the gate electrode of the MOSTFT 1 is formed.Next, after an overcoat film (a silicon oxide film or the like) 137 isformed by vapor-phase growth such as catalytic CVD, the drain electrode131 and a V_(dd) line of the MOSTFT 2 are formed by sputtering of aMo—Ta alloy or the like and by common photolithographic and etchingtechniques, and in addition, the overcoat film (a laminate of siliconoxide and silicon nitride) 136 is formed. By RTA (Rapid Thermal Anneal)treatment (for example, approximately 1,000° C. for 10 to 30 seconds)using a halogen lamp or the like, dopants, which have been ion-doped,are activated.

[0569] Next, as shown in FIG. 49(2), after windows are provided at thesource and the drain portions of the MOSTFT 1 and the gate portion ofthe MOSTFT 2, as shown in FIG. 49(3), by a sputtering film-formingtechnique using Al containing 1% Si and by common photolithographic andetching techniques, the drain of the MOSTFT 1 and the gate of the MOSTFT2 are connected to each other by the Al wire 128 containing 1% Si, andat the same time, the source line, which is formed of Al containing 1%Si and is connected to the source of the MOSTFT 1, is formed. Next, theovercoat film (a laminated film of silicon oxide, phosphine silicateglass, and silicon nitride, or the like) 130 is formed, andhydrogenating and sintering treatment is then performed. Subsequently, awindow is formed at the source portion of the MOSTFT 2 by commonphotolithographic and etching techniques, and the anode 144 in thelight-emitting portion connected to the source proton of the MOSTFT 2 isformed by sputtering of ITO or the like and common photolithographic andetching techniques.

[0570] Next, as shown in FIG. 49(4), the organic light-emitting layer132 or the like and the cathodes 141 and 142 are formed.

[0571] The materials forming the individual layers of the organic EL andthe manufacturing method therefor is applied to the example shown inFIG. 48 and, in addition, may be applied to the example shown in FIG.46.

[0572] In a conventional active matrix type organic El display deviceintegrated with a peripheral driving circuit, a pixel is identified byan X direction signal line and a Y direction signal line, and at theidentified pixel, a corresponding switching MOSTFT is turned on, so thatimage data is stored in a corresponding signal storing capacitor.Accordingly, a current controlling MOSTFT is turned on, a bias currentpasses through the organic EL element via a power supply line inaccordance with the image data, and emission is then performed. However,in the step described above, in the case of an amorphous silicon MOSTFT,the current is likely to vary due to the change in V_(th), and hence,the image quality tends to easily vary. In addition, since the carriermobility is low, driving current for high-speed response has beenlimited, and furthermore, since formation of a p-type channel has beendifficult, it has been difficult to manufacture a small-scale CMOScircuit configuration.

[0573] In contrast, according to the present invention described above,a polycrystalline silicon TFT having high reliability, high carriermobility, can be easily formed, the TFTs can be formed in a relativelylarge area, and a CMOS circuit configuration can be realized by this TFTdescribed above.

[0574] In addition, the individual green (G) organic light-emitting ELlayer, blue (B) organic light-emitting EL layer, and red (R) organiclight-emitting EL layer are formed having a thickness of 100 to 200 nm.When low molecular weight materials are used therefor, these organic ELlayers are formed by vacuum heating deposition, and when a polymermaterial is used, R, G, B light-emitting polymers are aligned by acoating method such as dip coating, spin coating, or roll coating, or anink-jet method.

[0575] As the organic EL layer, for example, there may be mentioned asingle layer type, a double-layer type, and a triple-layer type, and inthis embodiment, a triple-layer type using low molecular weightcompounds will be described by way of example.

[0576] Single-Layer; anode/bipolar light-emitting layer/cathode

[0577] Double-Layer; anode/hole transfer layer/electron transferlight-emitting layer/cathode, or anode/hole transfer light-emittinglayer/electron transfer layer/cathode

[0578] Triple-Layer; anode/hole transfer layer/light-emittinglayer/electron transfer layer/cathode, or anode/hole transferlight-emitting layer/carrier block layer/electron transferlight-emitting layer/cathode

[0579] When used for forming the green organic light-emitting EL layer,a low molecular weight compound is continuously processed by vacuumheating deposition to form the light-emitting layer mentioned above onan ITO transparent electrode, which is an anode (a hole injection layer)on a glass substrate, connected to the source portion of a currentdriving MOSTFT.

[0580] 1) A hole transfer layer is formed of an amine compound (such astiraryamine derivatives, arylamine oligomers, or aromatic triamines) orthe like.

[0581] 2) A light-emitting layer is formed of tris(8-hydroxyquinoline)Alcomplex (Alq), which is a green light-emitting material, or the like.

[0582] 3) An electron transfer layer is formed of 1,3,4-oxadiazolederivatives (OXD), 1,2,4-triazole derivatives (TAZ), or the like.

[0583] 4) An electron injection layer, which is a cathode, is preferablyformed of a material having a work function of 4 eV or less.

[0584] For example, a magnesium-silver alloy having an atomic ratio of10 to 1 and a thickness of 10 to 30 nm

[0585] an aluminum-Lithium (at a concentration of 0.5 to 1%) alloyhaving a thickness of 10 to 30 nm

[0586] In this embodiment, in order to increase the adhesion at theinterface between silver and an organic material, silver at a content of1 to 10 atom % is contained in magnesium, and in order to improve thestability, lithium at a concentration of 0.5 to 1% is contained inaluminum.

[0587] In order to form the green pixel portions, the green pixelportions are masked with a photoresist, the aluminum-lithium alloyforming an electron injection layer, which is used as cathodes, isremoved by plasma etching using CCl₄ or the like, and low molecularweight materials forming an electron transfer layer, a light-emittinglayer, and a hole transfer layer, and the photoresist, are continuouslyremoved by oxygen plasma etching, thereby forming the green pixelportions. In the steps described above, since the aluminum-lithium alloyis present under the photoresist, problems may not arise when thephotoresist is etched. In addition, in the steps described above, theareas of the low molecular weight compound layers forming the electrontransfer layer, the light-emitting layer, and the hole transfer layerare formed larger than that of the ITO transparent electrode, which isthe hole injection layer, so that electrical short-circuiting will notoccur with the cathode, i.e., the electron injection layer (amagnesium-silver alloy), which is formed over the entire surface in asubsequent step.

[0588] Next, when used for forming the blue organic light-emitting ELlayer, a low molecular weight compound is continuously processed byvacuum heating deposition to form the light-emitting layer mentionedabove on the ITO transparent electrode, which is the anode (a holeinjection layer) on the glass substrate, connected to the source portionof the current driving TFT.

[0589] 1) A hole transfer layer is formed of an amine compound (such astiraryamine derivatives, arylamine oligomers, or aromatic triamines) orthe like.

[0590] 2) A light-emitting layer is formed of a distyryl derivative,such as DTVBi which is a blue light-emitting material.

[0591] 3) An electron transfer layer is formed of 1,3,4-oxadiazolederivatives (OXD), 1,2,4-triazole derivatives (TAZ), or the like.

[0592] 4) An electron injection layer, which is a cathode, is preferablyformed of a material having a work function of 4 eV or less.

[0593] For example, a magnesium-silver alloy having an atomic ratio of10 to 1 and a thickness of 10 to 30 nm

[0594] an aluminum-lithium (at a concentration of 0.5 to 1%) alloyhaving a thickness of 10 to 30

[0595] In this embodiment, in order to increase the adhesion at theinterface between silver and an organic material, silver at a content of1 to 10 atom % is contained in magnesium, and in order to improve thestability, lithium at a concentration of 0.5 to 1% is contained inaluminum.

[0596] In order to form the blue pixel portions, the blue pixel portionsare masked with a photoresist, the aluminum-lithium alloy forming anelectron injection layer, which is used as cathodes, is removed byplasma etching using CCl₄ or the like, and low molecular weightmaterials forming an electron transfer layer, light-emitting layer, andhole transfer layer, and the photoresist, are continuously removed byoxygen plasma etching, thereby forming the blue pixel portions. In thesteps described above, since the aluminum-lithium alloy is present underthe photoresist, problems may not arise when the photoresist is etched.In addition, the areas of the low molecular weight compound layersforming the electron transfer layer, the light-emitting layer, and thehole transfer layer are formed larger than that of the ITO transparentelectrode, which is the hole injection layer, so that electricalshort-circuiting will not occur with the cathode, i.e., the electroninjection layer (a magnesium-silver alloy), which is formed over theentire surface in a subsequent step.

[0597] Next, when used for forming the red organic light-emitting ELlayer, a low molecular weight compound is continuously processed byvacuum heating deposition to form the light-emitting layer mentionedabove on the ITO transparent electrode, which is the anode (a holeinjection layer) on the glass substrate, connected to the source portionof the current driving TFT.

[0598] 1) A hole transfer layer is formed of an amine compound (such astiraryamine derivatives, arylamine oligomers, or aromatic triamines) orthe like.

[0599] 2) A light-emitting layer is formed of Eu(Eu(DBM)₃(Phen) or thelike.

[0600] 3) An electron transfer layer is formed of 1,3,4-oxadiazolederivatives (OXD), 1,2,4-triazole derivatives (TAZ), or the like.

[0601] 4) An electron injection layer, which is a cathode, is preferablyformed of a material having a work function of 4 eV or less.

[0602] For example, a magnesium-silver alloy having an atomic ratio of10 to 1 and a thickness of 10 to 30 nm

[0603] an aluminum-lithium (at a concentration of 0.5 to 1%) alloyhaving a thickness of 10 to 30 nm

[0604] In order to increase the adhesion at the interface between silverand an organic material, silver at a content of 1 to 10 atom % iscontained in magnesium, and in order to improve the stability, lithiumat a concentration of 0.5 to 1% is contained in aluminum.

[0605] In order to form the red pixel portions, the red pixel portionsare masked with a photoresist, the aluminum-lithium alloy forming anelectron injection layer, which is used as cathodes, is removed byplasma etching using CCl₄ or the like, and low molecular weightmaterials forming an electron transfer layer, light-emitting layer, andhole transfer layer, and the photoresist, are continuously removed byoxygen plasma etching, thereby forming the red pixel portions. In thesteps described above, since the aluminum-lithium alloy is present underthe photoresist, problems may not arise when the photoresist is etched.In addition, the areas of the low molecular weight compound layersforming the electron transfer layer, the light-emitting layer, and thehole transfer layer are formed larger than that of the ITO transparentelectrode, which is the hole injection layer, so that electricalshort-circuiting will not occur with the cathode, i.e., the electroninjection layer (a magnesium-silver alloy), which is formed over theentire surface in a subsequent step.

[0606] Subsequently, the electron injection layer, which is a commonelectrode, is formed over the entire surface by vacuum heatingdeposition, and this electron injection layer used as the cathode ispreferably formed from a material having a work function of 4 eV orless. For example, a magnesium-silver alloy having an atomic ratio of 10to 1 and having a thickness of 10 to 30 nm, or an aluminum-lithium (at aconcentration of 0.5 to 1%) having a thickness of 10 to 30 nm may beused. In this embodiment, in order to increase the adhesion at theinterface between silver and an organic material, silver at a content of1 to 10 atom % is contained in magnesium, and in order to improve thestability, lithium at a concentration of 0.5 to 1% is contained inaluminum. In addition, film formation may be performed by sputtering.

[0607] Fourth Embodiment

[0608] In this embodiment, the present invention is applied to a fieldemission type (FED) display devices. Hereinafter, the structuralexamples and the manufacturing examples thereof will be described. Inthis embodiment, a top gate type MOSTFT will be described, and it isnaturally understood that the present invention be applied to a bottomgate type or a dual gate type MOSTFT.

[0609] <Structural Example I of FED>

[0610] As shown in FIGS. 50(A), (B), and (C), according to thisstructural example I, by using the polycrystalline silicon thin-film,which may or may not contain tin and which has a large grain size andhigh crystallinity, formed by the method described above according tothe present invention on the substrate 111 composed of glass or thelike, the gate channel regions 117, the source regions 120, and thedrain regions 121 of the switching MOSTFT 1 and the current drivingMOSTFT 2 are formed. In addition, the gate electrodes 115 are formed onthe gate insulating film 118, and on the source and the drain regions,the source electrodes 127 and the drain electrode 128 are formed. Thedrain of the MOSTFT 1 is connected to the gate of the MOSTFT 2 via thedrain electrode 128, a capacitor C is formed between drain of the MOSTFT1 and the source electrode 127 of the MOSTFT 2 with the insulating film136 therebetween, and the drain region 121 of the MOSTFT 2 extends tothe FEC (Field Emission Cathode) of the FED element so as to serve asthe emitter region 152. In this case, an LDD portion may be formed inthe switching MOSTFT 1 so as to improve the switching properties.

[0611] The individual MOSTFTs are covered with the insulating film 130,on this insulating film, the metal shading film 151 is formed from thesame material and in the same step as those for the gate lead electrodes150 so as to cover the individual MOSTFTs. In the FEC, an n-typepolycrystalline silicon film 153, which is formed into field emissionemitters, is formed on the emitter region 152 composed of thepolycrystalline silicon thin-film, and the insulating films 118, 137,136, and 130 are patterned to form holes for defining m×n emitters, inwhich on the surfaces of the patterned insulating films, the gate leadelectrodes 150 are provided.

[0612] In addition, at the position opposing this FEC, a substrate 157,such as a glass substrate, provided with an anode composed of a backmetal 155 and a fluorescent material 156 is provided, and the spacebetween the FEC and the substrate is maintained at a high vacuum.

[0613] In the FEC having this structure, at the bottoms of the holesformed in the gate lead electrodes 150, the n-type polycrystallinesilicon film 153 grown on the polycrystalline silicon thin-film 152formed according to the present invention is exposed, these areas at thebottom of the holes each serve as a surface emission thin-film emitteremitting electrons 154. That is, since the polycrystalline siliconthin-film 152 used as an underlayer of the emitter is formed of grainshaving a large diameter (a grain size of several hundred nanometers ormore), when the n-type polycrystalline silicon film 153 is grown bycatalytic CVD or the like using this underlayer as a seed, thispolycrystalline silicon film 153 is also grown so as to have largergrains and is formed so as to have irregularities on the surface, whichare advantages for emitting electrons. In addition to that describedabove, electron emitting material may be formed of a polycrystallinediamond film, a carbon thin-film which may or may not contain nitrogen,a number of minute protruding structures (for example, carbon nanotube)formed on a surface of a carbon thin-film which may or may not containnitrogen.

[0614] Accordingly, since the emitter is a surface emission typethin-film, the formation thereof is easily performed, and in addition,the emitter properties are stable, thereby achieving a longer life.

[0615] In addition, since the metal shielding film 151 (this metalshielding film is preferably formed from the same material (Nb, Ti/Mo,or the like) and in the same step as those for the lead gate electrodes150 in view of a manufacturing process) at the earth potential is formedover all the active elements (including the MOSTFTs and diodes in theperipheral driving circuit and the pixel display portions), theadvantages (1) and (2) described below can be obtained, and a highquality and highly reliable field emission display (FED) can berealized.

[0616] (1) A gas in an air-tight container is positively charged byelectrons emitted from the emitter (field emission cathode) 153 and ischarged-up on an insulating film, this positive charges form anunnecessary conversion layer in the MOSTFT under the insulating layer,and an excessive current flows through an unnecessary current pathformed of this conversion layer, resulting in an abrupt increase inemitter current. However, since the metal shielding film 151 is formedon the insulating layer provided on the MOSTFTs and is grounded to theearth, the charge-up can be prevented, and hence, an abrupt increase inemitter current can be prevented.

[0617] (2) The fluorescent material 156 emits light by collision ofelectrons emitted from the emitter (field emission cathode) 153;however, by the light mentioned above, electron and holes are generatedin the gate channels of MOSTFTs, resulting in generation of leakagecurrent. However, since the metal shielding film 151 is formed on theinsulating layer provided on the MOSTFTs, entry of light into the TFTscan be prevented, and hence, operational defects of the TFTs do notoccur.

[0618] Next, a process for manufacturing this FED will be described.First, as shown in FIG. 51 (1), after the polycrystalline siliconthin-film 117 is formed over the entire surface by the steps describedabove, islands for the MOSTFT 1, the MOSTFT 2, and the emitter regionare formed by common photolithographic and etching techniques, and asilicon oxide film 159 for protection is formed over the entire surfaceby plasma CVD, catalytic CVD, or the like. Related to this, after theformation of the silicon oxide film for protection, islands may beformed.

[0619] Next, to optimize the V_(th) by the control of dopantconcentrations in the gate channels of the MOSTFTs 1 and 2, boron ions83 are doped into the entire surface thereof at a dose rate of 5×10¹¹atoms/cm² by ion implantation or ion doping so as to have an acceptorconcentration of 1×10¹⁷ atoms/cc.

[0620] Next, as shown in FIG. 51(2), by using the photoresist 82 as amask, phosphorus ions 79 are doped into the source and the drain regionsof the MOSTFTs 1 and 2 and the emitter region at a dose rate of 1×10¹⁵atoms/cm² by ion implantation or ion doping so as to have a donorconcentration of 2×10²⁰ atoms/cc, thereby forming the source regions120, drain regions 121, and emitter region. 152. Subsequently, by commonphotolithographic and etching techniques, the silicon oxide film forprotection in the emitter region is removed. In the step describedabove, an LDD region having a donor concentration of (1 to 5)×10¹⁸atoms/cc may be formed so as to improve the switching properties.

[0621] Next, as shown in FIG. 51(3), by using the polycrystallinesilicon thin-film 152 which forms the emitter region as a seed, then-type polycrystalline silicon film 153, having a thickness of 1 to 5 μmand minute irregularities 158 on the surface thereof, is formed in theemitter region by catalytic CVD or bias catalytic CVD using a mixture ofmonosilane and dopant such as PH₃ at an appropriate ratio (for example,10²⁰ atoms/cc), and at the same time, an n-type amorphous silicon film160 having a thickness of 1 to 5 μm is formed on the other silicon oxidefilm 159 and the glass substrate 111.

[0622] Next, as shown in FIG. 51(4), by activated hydrogen ions or thelike in catalytic AHA treatment described above, the amorphous siliconfilm 160 is selectively removed by etching, and after the silicon oxidefilm 159 is removed by etching, the gate insulating film (a siliconoxide film) 118 is formed by catalytic CVD or the like.

[0623] Next, as shown in FIG. 52(5), the gate electrodes 115 of theMOSTFTs 1 and 2 and a gate line connected to the gate electrode of theMOSTFT 1 are formed by sputtering of a heat resistant metal, such as anMo—Ta alloy, and after the overcoat film (a silicon oxide film or thelike) 137 is formed, by RTA (Rapid Thermal Anneal) treatment using ahalogen lamp or the like, the n-type or the p-type dopant, which hasbeen doped previously, is activated. Next, after forming windows at thesource portion of the MOSTFT 2, the source electrode 127 of the MOSTFT 1and an earth line are formed by sputtering of a heat resistant metal,such as an Mo—Ta alloy. Furthermore, the overcoat film (a laminated filmof silicon oxide and silicon nitride or the like) 136 is formed byplasma CVD, catalytic CVD, or the like.

[0624] Next, as shown in FIG. 52(6), after windows are provided at thesource and the drain portions of the MOSTFT 1 and the gate portion ofthe MOSTFT 2, the drain of the MOSTFT 1 and the gate of the MOSTFT 2 areconnected to each other by the Al wire 128 containing 1% Si, and at thesame time, the source electrode of the MOSTFT 1 and a source line 127,which is connected to this electrode, are formed. Next, hydrogenationand sintering treatment is performed at 400° C. for 30 minutes in aforming gas.

[0625] Next, as shown in FIG. 52(7), after the overcoat film (alaminated film of silicon oxide, phosphine silicate glass, and siliconnitride, or the like) 130 is formed, a window is formed for a GND line,and as shown in FIG. 52(8), the lead electrodes 150 and the metalshielding film 151 are formed by Nb deposition followed by etching, theemitters 153 are exposed by forming windows in the field emissioncathode portion, and cleaning is then performed by activated hydrogenions or the like formed by plasma or catalytic AHA treatment describedabove.

[0626] A conventional field emission display device (FED) is roughlyclassified into passive-matrix and active-matrix drive. As the fieldemitter, for example, there may be mentioned a spintdt type molybdenumemitter, a corn type silicon emitter, an MIM tunnel emitter, a poroussilicon emitter, a diamond emitter, or a surface conduction emitter, andeach emitter mentioned above may be collectively formed on a planesubstrate. In the passive-matrix drive, a field emitter array disposedin the X-Y matrix is used as one pixel, and image display is performedby adjusting an emission amount of each pixel. In the active-matrixdrive, an emission current of an emitter formed at the drain portion ofa MOSTFT is controlled by a control gate. Since a process for formingthis drive system is compatible with that for common silicon LSIs, acomplicated processing circuit can be easily formed at the periphery ofthe field emission display device. However, since silicon singlecrystalline wafers are used, the substrate cost is high, and it has beendifficult to form a display device having an area larger than the wafersize. A method has been proposed in which a conductive polycrystallinesilicon is formed on a cathode surface by reduced-pressure CVD or thelike, and on the surface thereof, an emitter composed of a crystallinediamond film formed by plasma CVD or the like is formed. However since adeposition temperature in reduced-pressure CVD is high such as 630° C.,a low strain point glass cannot be used, and hence, cost reductioncannot be easily performed. In addition, a polycrystalline silicon filmformed by the reduced-pressure has a small grain size, the crystallinediamond formed thereon also has a small grain size, and hence, theemitter properties are not good. Furthermore, sufficient reaction energycannot be obtained by plasma CVD, it is difficult to form a diamond filmhaving good crystallinity. In addition, since the matching propertiesbetween the conductive polycrystalline silicon film and a transparentelectrode or a cathode formed of a metal, such as Al, Ti, or Cr, are notgood, superior emission properties cannot be obtained.

[0627] In contrast, the polycrystalline silicon thin-film having a largegrain size formed according to the present invention can be formed on asubstrate such as a low strain point glass and is formed in the emitterregion connected to the drain of the current driving TFT, and by usingthis polycrystalline silicon thin-film as a seed, the emitters composedof the n-type (or n⁺-type) polycrystalline silicon film (or thepolycrystalline diamond film described below) having a large grain sizecan be formed. In addition, by continuously and selectively etching theamorphous silicon film or an amorphous diamond film (DLC: Diamond LikeCarbon) by reduction in catalytic AHA treatment or the like, an n-type(or n⁺-type) polycrystalline silicon film, having high crystallinity anda large grain size, provided with an infinitude of irregularities on thesurface is formed, and hence, emitters having superior electron emissionefficiency can be formed. Furthermore, the matching properties betweenthe drain and the emitter are superior, and hence, highly efficientemitter properties can be obtained. Accordingly, the conventionalproblems described above can be solved (hereafter, the same as above).

[0628] In addition, when the emitter region in one pixel display portionis divided into a plurality of areas, and a MOSTFT, which is a switchingelement, is connected to each area, even if one MOSTFT is out of order,since the other MOSTFTs work, electron emission is always performed inone pixel display portion. Accordingly, a high quality FED can bemanufactured at high yield, and cost reduction can be realized(hereafter, the same as described above). As a general measure forimproving the yield, among these MOSTFTs mentioned, a MOSTFT having adisconnection defect may not be a problem, and a MOSTFT having ashort-circuiting defect is recovered by separation using laser repair.Since this measure can be applied to the above configuration accordingto the present invention, a high quality FED can be manufactured at highyield, and cost reduction can be realized (hereafter, the same asdescribed above).

[0629] <Structural Example II of FED>

[0630] As shown in FIGS. 53(A), (B), and (C), according to thisstructural example II, as is the structural example I described above,by using the polycrystalline silicon thin-film, which may or may notcontain tin and which has a large grain size and high crystallinity,formed by the method described above according to the present inventionon the substrate 111 composed of glass or the like, the gate channelregions 117, the source regions 120, and the drain regions 121 of theswitching MOSTFT 1 and the current driving MOSTFT 2 are formed. Inaddition, the gate electrodes 115 are formed on the gate insulating film118, and on the source and the drain regions, the source electrodes 127and the drain electrode 128 are formed. The drain of the MOSTFT 1 isconnected to the gate of the MOSTFT 2 via the drain electrode 128, thecapacitor C is formed between the drain of the MOSTFT 1 and the sourceelectrode 127 of the MOSTFT 2 with the insulating film 136 therebetween,and the drain region 121 of the MOSTFT 2 extends to the FEC (FieldEmission Cathode) of the FED element so as to serve as the emitterregion 152. In this case, an LDD portion may be formed in the switchingMOSTFT 1 so as to improve the switching properties.

[0631] The individual MOSTFTs are covered with the insulating film 130,on this insulating film, the metal shading film 151 is formed from thesame material and in the same step as those for the gate lead electrodes150 so as to cover the individual MOSTFTs. In the FEC, an n-typepolycrystalline diamond film 163, which is formed into field emissionemitters, is formed on the emitter region 152 composed of thepolycrystalline silicon thin-film, and the insulating films 118, 137,136, and 130 are patterned to form holes for defining m×n emitters, inwhich on the surfaces of the patterned insulating films, the gate leadelectrodes 150 are provided.

[0632] In addition, at the position opposing this FEC, the substrate157, such as a glass substrate, provided with the anode composed of theback metal 155 and the fluorescent material 156 is provided, and thespace between the FEC and the substrate is maintained at a high vacuum.

[0633] In the FEC having this structure, at the bottoms of the holesformed in the gate lead electrodes 150, the n-type polycrystallinediamond film 163 grown on the polycrystalline silicon thin-film 152,which is formed according to the present invention, is exposed, theseareas at the bottom of the holes serve as surface emission thin-filmemitters emitting electrons 154. That is, since the polycrystallinesilicon thin-film 152 used as an underlayer of the emitter is formed ofgrains having a large diameter (a grain size of several hundrednanometers or more), when the n-type polycrystalline diamond film 163 isgrown by catalytic CVD or the like using this underlayer as a seed, thispolycrystalline diamond film 163 is also grown so as to have a largergrain and is also formed so as to have irregularities, which areadvantages of electron emission, on the surface thereof. In addition tothat described above, the emitter may be formed of a carbon thin-filmwhich may or may not contain nitrogen, or a number of minute protrudingstructures (for example, carbon nanotube) formed on a surface of acarbon thin-film which may or may not contain nitrogen.

[0634] Accordingly, since the emitter is a surface emission thin-film,the formation thereof is easily performed, and in addition, the emitterproperties are stable, thereby achieving a longer life.

[0635] In addition, since the metal shielding film 151 (this metalshielding film is preferably formed from the same material (Nb, Ti/Mo,or the like) and in the same step as those for the lead gate electrodes150 in view of a manufacturing process) at the earth potential is formedover all the active elements (including the MOSTFTs and diodes in theperipheral driving circuit and the pixel display portion), as is thecase of the described above, the insulating layer provided on theMOSTFTs is grounded to the earth by the metal shielding film 151 thusformed, and hence, charge-up can be prevented and an abrupt increase inemitter current can also be prevented. In addition, since the metalshielding film 151 is provided on the insulating layer on the MOSTFTS,entry of light into the MOSTFTs can be prevented, and hence, operationdefects of the MOSTFTs do not occur. Accordingly, a high quality andhighly reliable field emission display (FED) can be realized.

[0636] Next, a process for manufacturing this FED will be described.First, as shown in FIG. 54 (1), after the polycrystalline siliconthin-film 117 is formed over the entire surface by the steps describedabove, islands are formed for the MOSTFT 1, the MOSTFT 2, and theemitter region by common photolithographic and etching techniques, andthe silicon oxide film 159 for protection is formed over the entiresurface by plasma CVD, catalytic CVD, or the like. Related to this,after the formation of the silicon oxide film for protection, islandsmay be formed.

[0637] Next, to optimize the V_(th) by the control of dopantconcentrations in the gate channels of the MOSTFTs 1 and 2, boron ions83 are doped into the entire surface thereof at a dose rate of 5×10¹¹atoms/cm² by ion implantation or ion doping so as to have an acceptorconcentration of 1×10¹⁷ atoms/cc.

[0638] Next, as shown in FIG. 54(2), by using the photoresist 82 as amask, phosphorus ions 79 are doped into the source and the drain regionsof the MOSTFTs 1 and 2 and the emitter region at a dose rate of 1×10¹⁵atoms/cm² by ion implantation or ion doping so as to have a donorconcentration of 2×10²⁰ atoms/cc, thereby forming the source regions120, drain regions 121, and emitter region 152. Subsequently, by commonphotolithographic and etching techniques, the silicon oxide film forprotection in the emitter region is removed.

[0639] Next, as shown in FIG. 54(3), by using the polycrystallinesilicon thin-film 152 forming the emitter region as a seed, the n⁺-typepolycrystalline diamond film 163, having minute irregularities 168 onthe surface thereof, is formed in the emitter region by catalytic CVD orbias catalytic CVD using a mixture of, for example, methane (CH₄) and anappropriate n-type dopant at an appropriate mixing ratio, and at thesame time, an n⁺-type amorphous diamond film 170 is formed on the othersilicon oxide film 159 and the glass substrate 111. For example, then⁺-type polycrystalline diamond film 163 is formed by catalytic CVD orthe like using the polycrystalline silicon thin-film 152 having a largegrain size, and in this step, by adding an n-type doping gas (phosphinePH₃ for phosphorus, arsine AsH₃ for arsenic, stibine SbH₃ for antimony,or the like) such as phosphine PH₃ to methane (CH₄) at an appropriateamount, the n⁺-type polycrystalline diamond film 163 (1,000 to 5,000 mmthick) having a dopant concentration of approximately 5×10²⁰ to 1×10²¹atoms/cc is formed. In the step described above, on the other siliconoxide film for protection, the n⁺-type amorphous diamond film 170 isformed, and this amorphous diamond film is also called a DLC film(Diamond Like Carbon).

[0640] Next, as shown in FIG. 54(4), by activated hydrogen ions or thelike in catalytic AHA treatment described above, the amorphous diamondfilm 170 is selectively removed by etching, and after the silicon oxidefilm 159 is removed by etching, the gate insulating film (a siliconoxide film or the like) 118 is formed by catalytic CVD or the like. Inthe steps described above, by catalytic AHA treatment, the amorphousdiamond film is selectively etched by reduction using high temperaturehydrogen molecules, hydrogen atoms, activated hydrogen ions, or thelike, and at the same time, an amorphous component of the n⁺-typepolycrystalline diamond film 163 formed in the emitter region isselectively etched by reduction, thereby forming the n⁺-typepolycrystalline diamond film 163 having high crystallinity. By thisselective etching by reduction, the emitter region composed of then⁺-type polycrystalline diamond film 163 having an infinitude ofirregularities on the surface thereof is formed. By the step describedabove, the n⁺-type amorphous diamond film on the other silicon oxidefilm for protection is selectively etched by reduction. Related to this,it is preferable that the catalytic CVD and the AHA treatment becontinuously performed in order to prevent contamination and to improveproductivity.

[0641] Next, as shown in FIG. 55(5), the gate electrodes 115 of theMOSTFTs 1 and 2 and the gate line connected to the gate electrode of theMOSTFT 1 are formed by sputtering of a heat resistant metal, such as anMo—Ta alloy, and after the overcoat film (a silicon oxide film or thelike) 137 is formed, by RTA (Rapid Thermal Anneal) treatment using ahalogen lamp, the n-type or the p-type dopant doped previously isactivated. Next, after forming a window at the source portion of theMOSTFT 2, the source electrode 127 of the MOSTFT 2 and the earth lineare formed by sputtering of a heat resistant metal, such as an Mo—Taalloy. Furthermore, the overcoat film (a laminated film of silicon oxideand silicon nitride, or the like) 136 is formed by plasma CVD, catalyticCVD, or the like.

[0642] Next, as shown in FIG. 55(6), after windows are provided at thesource and the drain portions of the MOSTFT 1 and the gate portion ofthe MOSTFT 2, the drain of the MOSTFT 1 and the gate of the MOSTFT 2 areconnected to each other by the Al wire 128 containing 1% Si, and at thesame time, the source electrode of the MOSTFT 1 and the source line 127,which is connected to this electrode, are formed.

[0643] Next, as shown in FIG. 55(7), after the overcoat film (alaminated film of silicon oxide, phosphine silicate glass, and siliconnitride, or the like) 130 is formed, and a window is then formed for theGND line, hydrogenating and sintering treatment is performed at 400° C.for 30 minutes in a forming gas. Subsequently, as shown in FIG. 55(8),the lead electrodes 150 and the metal shielding film 151 are formed byNb deposition followed by etching, the emitters 163 are exposed byforming windows at the field emission cathode portion, and cleaning isthen performed by activated hydrogen ions or the like formed bycatalytic AHA treatment described above. That is, by commonphotolithographic and etching techniques, a laminated film of titaniumand molybdenum (Ti/Mo) or a niobium (Nb) film is wet-etched using anacidic etching solution, a silicon oxide film and a PSG film are etchedusing a fluorinated etching solution, and a silicon nitride film isremoved by plasma etching using CF₄ or the like. In addition, thepolycrystalline diamond film 163 of the field emission cathode (emitter)portion is cleaned by catalytic AHA treatment so that organiccontamination, moisture, oxygen, nitrogen, carbon dioxide, or the like,which adhere to the minute irregularities on the film surface, areremoved by high temperature hydrogen molecules, hydrogen atoms,activated hydrogen ions, or the like formed by catalytic AHA treatment,thereby improving the electron emission efficiency.

[0644] In addition, in the case described above, when thepolycrystalline diamond film 163 is formed, as a carbon-containingcompound used as a source gas, there may be mentioned, for example,

[0645] 1) a paraffinic hydrocarbon, such as methane, ethane, propane, orbutane;

[0646] 2) an acetylenic hydrocarbon, such as acetylene or allylene-basedmaterial;

[0647] 3) an olefinic hydrocarbon, such as ethylene, propylene, orbutylene;

[0648] 4) a diolefinic hydrocarbon such as butadiene;

[0649] 5) an alicyclic hydrocarbon, such as cyclopropane, cyclobutane,cyclopentane, or cyclohexane;

[0650] 6) an aromatic hydrocarbon, such as cyclobutadiene, benzene,toluene, xylene, or naphthalene;

[0651] 7) a ketone, such as acetone, diethyl ketone, or benzophenone;

[0652] 8) an alcohol, such as methanol or ethanol;

[0653] 9) an amine, such as trimethyl amine or triethyl amine;

[0654] 10) a material containing only carbon atoms, such as graphite,coal, or coke. There materials may be used alone or in combination.

[0655] In addition, as a usable inert gas, for example, argon, helium,neon, krypton, xenon, and radon are mentioned. As a dopant, for example,boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsenic,selenium, beryllium, or the compound thereof may be used, and the dopingamount may be 10¹⁷ atoms/cc or more.

[0656] Fifth Embodiment

[0657] In this embodiment, the present invention is applied to a solarcell which is a photoelectric transfer device. A manufacturing examplethereof will be described below.

[0658] First, as shown in FIG. 56(1), the n-type low-crystallizationsilicon film 7A (100 to 200 nm thick) is formed by plasma CVD, catalyticCVD, or the like on the metal substrate 111 formed of stainless steel orthe like. In this case, an n-type dopant such as PH₃ is appropriatelycontained in monosilane so as to have a concentration of 1×10¹⁹ to1×10²⁰ atoms/cc. In addition, when necessary, a thin-film (100 to 300 nmthick) of a high melting point metal (Ti, Ta, Mo, W, or an alloythereof, such as a Mo—Ta alloy) or a metal silicide (WSi₂, MoSi₂, TiSi₂,TaSi₂, or the like) is formed on the metal substrate or a glasssubstrate by sputtering, CVD, or the like.

[0659] Continuously, by plasma CVD, catalytic CVD, or the like, ani-type low-crystallization silicon film 180A (2 to 5 μm thick) is formedso as to have a laminated structure. Continuously, by plasma CVD,catalytic CVD, or the like, a p-type low-crystallization silicon film181A (100 to 200 nm thick) is formed. In this case, a p-type dopant suchas B₂H₆ is appropriately contained in monosilane so as to have aconcentration of 1×10¹⁹ to 1×10²⁰ atoms/cc.

[0660] Next, as shown in FIG. 56(2), by plasma CVD, catalytic CVD, orthe like, a covering, insulating film 235 (a silicon oxide film, asilicon nitride film, a silicon oxinitride film, a laminated film ofsilicon oxide and silicon nitride, or the like) having a thickness of 50to 100 nm is formed.

[0661] Next, by annealing by flash emission 221 from flash lampsperformed in the state described above, the entire low-crystallizationsilicon films 7A, 180A, and 181A are converted into the polycrystallinesilicon film 7, 180, and 181, and simultaneously, the dopants in theindividual films are activated. In this step, in accordance with thethickness of the low-crystallization silicon film, flash emission isperformed repeatedly as required for a long flash emission time (⅓ pulsewidth=1.5 milliseconds or more). However, flash emission conditions mustbe optimized by, for example, using no IR-blocking filter, increasing asetting temperature, or the like.

[0662] Next, as shown in FIG. 56(3), the covering, insulating film 235is removed, and hydrogenating treatment is then performed at 400° C. for1 hour in a forming gas. Subsequently, a transparent electrode (ITO(Indium Tin Oxide), IZO (Indium Zinc Oxide), or the like) 182 having athickness of 100 to 150 nm is formed over the entire surface, and onthis film thus formed, a comb electrode 183, which is composed of, forexample, silver, and has a thickness of 100 to 150 mm, is formed in apredetermined region by using a metal mask.

[0663] In addition, by adding an appropriate amount of Sn or anotherGroup IV element (Ge, or Pb) to the low-crystallization silicon film 7A,180A, and 181A so as to have a concentration in the range of, forexample, 1×10¹⁸ to 1×10²⁰ atoms/cc, irregularity present at thepolycrystalline boundaries and film stress may be reduced.

[0664] In the solar cell of this embodiment, since a photoelectrictransfer thin-film having high mobility and transfer efficiency can beformed from the polycrystalline silicon film having a large grain sizeaccording to the present invention, and a superior surface texturestructure and rear surface texture structure are formed, a photoelectrictransfer thin-film having a high light enclosing effect and conversionefficiency can be formed. In addition to the solar cell, thisphotoelectric thin-film can be advantageously applied to thin-filmphotoelectric devices such as a photosensitive drum forelectrophotograph.

[0665] Other Embodiments

[0666]FIG. 57 is a graph for illustrating a method for forming asemiconductor thin-film or a method for manufacturing a semiconductordevice by showing the sequence from a first step to a fourth step. Themethod mentioned above comprises the first step of forming alow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; thesecond step of heating the substrate to a strain temperature thereof orless in pre-baking; the third step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state to facilitate the crystallization thereof by flashlamp annealing in assist-baking; and the fourth step of heating thecrystallized semiconductor thin-film until the temperature thereof isdecreased to the stain point of the substrate or less. These steps arepreferably repeated.

[0667] In the pre-baking described above, it is preferable that thetemperature be in the range of room temperature to a strain temperatureof the substrate, for example, from 300 to 500° C., by heating meanssuch as a resistance heater or a halogen lamp, and that the heating timebe optimized, for example, 5 to 20 minutes, in accordance with the filmthickness and the film quality, determined by conditions (vapor-phasegrowth, sputtering, deposition, or the like) for forming thelow-crystallization semiconductor thin-film, and a material, size, orthe like of the substrate.

[0668] In addition, in the assist-baking described above, it ispreferable that the temperature be in the range of room temperature tothe strain temperature of the substrate, for example, from 300 to 500°C., and be optimized in accordance with the flash lamp annealingconditions, the film thickness and the film quality, determined byconditions (vapor-phase growth, sputtering, deposition, or the like) forforming the low-crystallization semiconductor thin-film, and a material,size, or the like of the substrate.

[0669] In addition, in the post-baking described above, it is preferablethat the substrate and the crystallized semiconductor thin-film be heldfor a certain period of time, for example, 1 to 10 minutes, until thetemperature thereof is decreased at least to the pre-baking temperatureor the assist-baking temperature.

[0670]FIG. 58 is a schematic view for illustrating a method for forminga semiconductor thin-film or a method for manufacturing a semiconductordevice. When a shading underlying film 301, which has thermal andelectrical conductivities higher than those of the substrate, and whichhighly absorbs flash emission light or highly reflects the flashemission light, the flash emission light passing through areflection-reducing, protective, insulating film 300 and thelow-crystallization semiconductor thin-film 7A, is formed on thesubstrate 1 so as to have an area equivalent to or larger that that ofthe low-crystallization semiconductor thin-film 7A, and in addition,when a shading buffer film 302 having electrical insulating propertiesand transmittance properties is formed on the underlying layer whennecessary, the method mentioned above comprises a step of forming thelow-crystallization semiconductor thin-film 7A which may or may notcontain at least one Group IV element such as tin on the buffer film inthe underlying film region; a step of, when necessary, forming areflection-reducing, protective, insulating film 300; a step of heatingand cooling the low-crystallization semiconductor thin-film to a fusion,a semi-fusion, or a non-fusion state by appropriate flash lamp annealingof the substrate 1 in pre-baking, assist-baking, and post-baking so asto facilitate the crystallization of the low-crystallizationsemiconductor thin-film 7A.

[0671] When a bottom gate TFT, a back gate TFT, a dual gate TFT, or thelike is formed, as a material for forming the high thermal andelectrical conductive underlying film 301, which absorbs light passingthrough the reflection-reducing, protective, insulating film and thelow-crystallization semiconductor thin-film and is heated thereby, forexample, a coloring metal (chromium, copper, or the like), a highmelting point metal (titanium, tantalum, molybdenum, tungsten, an alloythereof, such as a molybdenum-tantalum alloy, or the like), or a metalsilicide (WSi₂, MoSi₂, TiSi₂, TaSi₂, CoSi, Pd₂Si, Pt₂Si, CrSi₂, NiSi,RhSi, or the like) may be used. In this case, since the substratetemperature is increased to a relatively high level, a high strain point(heat resistant) glass such as quartz glass or crystallized glass, or aceramic may be suitably used as a material for forming the substrate 1.

[0672] As a material for forming the high thermal and electricalconductive underlying film 301, which reflects light passing through thereflection-reducing, protective, insulating film and thelow-crystallization semiconductor thin-film, for example, white colormetal {aluminum, an aluminum alloy (aluminum containing 1% silicon),silver, nickel, platinum, or the like}, or a laminated film of whitecolor metal and a high melting point metal (aluminum/molybdenum or thelike) may be used. In this case, since the substrate temperature isincreased to a relatively low level, a low strain point glass, such asborosilicate glass, aluminosilicate glass, or reinforced glass may besuitably used; however, a high strain point (heat resistant) glass, suchas quartz glass or crystallized glass, a ceramic, or the like may alsobe used.

[0673] In order to prevent reaction between the underlying film 301 andthe fused low-crystallization semiconductor thin-film 7A, the bufferfilm 302 is formed; however, when the underlying film 301 is formed of amaterial that will not react with the fused low-crystallizationsemiconductor thin-film 7A, the buffer film may be omitted. For example,when the underlying film is formed of aluminum covered with anodizedinsulating film, a high melting point metal (an Mo—Ta alloy or thelike), or the like, the formation of an additional buffer film 302 isnot necessary.

[0674] As the buffer film 302, an electrical insulating silicon oxidefilm, silicon oxinitride film, silicon nitride film, laminated filmcomposed of silicon oxide and silicon nitride, laminated film composedof silicon nitride and silicon oxide, laminated film composed of siliconoxide, silicon nitride, and silicon oxide, or the like may be used.

[0675] As the substrate 1, when a low strain point glass such asborosilicate glass or aluminosilicate glass, fused quartz glass,crystallized glass, or a heat resistant resin is used, in order toprevent the diffusion of impurities (Na ions or the like) from thesubstrate, a silicon nitride-based film, such as a silicon oxinitridefilm, a silicon nitride film, a laminated film composed of silicon oxideand silicon nitride, a laminated film composed of silicon nitride andsilicon oxide, or a laminated film composed of silicon oxide, siliconnitride, and silicon oxide, is preferably used.

[0676] In this example, by forming the low-crystallization semiconductorthin-film 7A only in the underlying film region, fused silicon isprevented from flowing out, and the polycrystalline or the singlecrystalline silicon thin-film can be formed only in the underlying filmregion.

[0677]FIG. 59 shows an example in which the underlying film 301 ispatterned so as to have the area equivalent to or larger than that ofthe low-crystallization semiconductor thin-film 7A which may or may notcontain at least one Group IV element such as tin and to have a linearlyprotruding shape 301A at a part of the underlying film. In this example,heat of the low-crystallization semiconductor thin-film 7A in a fusion,a semi-fusion, or a non-fusion state by flash lamp annealing isdissipated from this projecting portion 301A to form nuclei for crystalgrowth, so that the entire thin-film can be crystallized in an optionalorientation direction.

[0678] In this case, since heat dissipation at the projecting portion301 is more efficiently performed than that at the other portions, andconditions (formation of species or nuclei), which may startrecrystallization, are prepared thereby, the entire low-crystallizationsemiconductor thin-film may be converted into the polycrystallinesemiconductor thin-film having a large grain size or the singlecrystalline semiconductor thin-film 7, each having an optional crystalorientation.

[0679] In addition, the reflection-reducing, protective, insulating film300 is an electrical insulating film which at least transmitsultraviolet rays therethrough and may be used as a gate insulating film.

[0680] As the electrical insulating film which at least transmitsultraviolet rays therethrough, for example, there may be mentioned asilicon oxide film, a silicon nitride film, a silicon oxinitride film, alaminated film composed of silicon oxide and silicon nitride, alaminated film composed of silicon nitride and silicon oxide, or alaminated film composed of silicon oxide, silicon nitride, and siliconoxide, and as the gate insulating film, there may be mentioned, forexample, a silicon oxide film, a silicon nitride film, a siliconoxinitride film, a laminated film composed of silicon oxide and siliconnitride, a laminated film composed of silicon nitride and silicon oxide,or a laminated film composed of silicon oxide, silicon nitride, andsilicon oxide.

[0681] In the example shown in FIG. 59, the reflection-reducing,protective, insulating film 300 may also be used as the gate insulatingfilm. For example, when the low-crystallization semiconductor thin-film7A which may or may not contain at least one Group IV element such astin is converted into the crystal 7 by heating and cooling the thin-filmto a fusion, a semi-fusion, or a non-fusion state in flash lampannealing in an oxidizing atmosphere (air, oxygen, ozone, steam, NO,N₂O, or the like), the oxide insulating film (a silicon oxide film, asilicon oxinitride film, or the like) 300 is simultaneously formed onthe surface of this polycrystalline or single crystalline semiconductorthin-film, and this oxide insulating film may be used as the gateinsulating film or the protection film.

[0682] Alternatively, on the polycrystalline or single crystallinesemiconductor thin-film, which may or may not contain at least one GroupIV element such as tin and which is formed by flash lamp annealing on alow strain point glass substrate, a high strain point glass substrate,or a heat resistant resin substrate 1, the oxide insulating film (asilicon oxide film, a silicon nitride film, or the like) 300 may beformed in an oxidizing atmosphere (air, oxygen, ozone, steam, NO, N₂O,or the like) at low temperature in the range of room temperature to thestrain point of the substrate and at a pressure in the range of 0.1 to30 MPa, and this oxide insulating film may be used as the gateinsulating film or the protection film.

[0683] Alternatively, on the polycrystalline or single crystallinesemiconductor thin-film which may or may not contain at least one GroupIV element such as tin and which is formed by flash lamp annealing on ahigh strain point glass substrate, the oxide-based insulating film (asilicon oxide film, a silicon nitride film, or the like) 300 may beformed by high temperature thermal oxidation in an oxidizing atmosphere(air, oxygen, ozone, steam, NO, N₂O, or the like), and this oxideinsulating film may be used as the gate insulating film or theprotection film.

[0684] Alternatively, on the polycrystalline or single crystallinesemiconductor thin-film, which may or may not contain at least one GroupIV element such as tin, which is provided with the reflection-reducing,protective, insulating film, and which is formed by flash lamp annealingon a high strain point glass substrate, the oxide-based insulating film(a silicon oxide film, a silicon nitride film, or the like) 300 may beformed by high temperature thermal oxidation in an oxidizing atmosphere(air, oxygen, ozone, steam, NO, N₂O, or the like), and this oxideinsulating film may be used as the gate insulating film or theprotection film.

[0685] The embodiments described above may be variously modified inaccordance with the technical scope and spirit of the present invention.

[0686] For example, the vapor-phase growth method, such as catalytic CVDor plasma CVD, and the various conditions, such as the number of flashlamp annealing performed repeatedly, the flash emission time, thesurface temperature, and the like may be variously changed, and thematerials for the substrate or the like are not limited to thosedescribed above.

[0687] In addition, the present invention is preferably applied toMOSTFTs for internal circuits, peripheral driving circuits, image signalprocessing circuits, memory circuits, and the like in the displayportions or the like; however, in addition to those described above,active regions for elements such as diodes, and passive regions forresistors, capacitors (capacitance), wires, inductances, and the likemay be formed of the polycrystalline semiconductor thin-film or thesingle crystalline semiconductor thin-film of the present invention.

[0688] Industrial Applicability

[0689] As described above, according to the present invention, since apolycrystalline or a single crystalline semiconductor thin-film isformed by forming a low-crystallization semiconductor thin-film on asubstrate and by heating and cooling the low-crystallizationsemiconductor thin-film to a fusion, a semi-fusion, or a non-fusionstate by flash lamp annealing to facilitate the crystallization thereof,the significant advantages (1) to (10) described below can be obtained.

[0690] (1) By flash lamp annealing in which flash emission can beperformed once or repeatedly in an optional short period of time in therange of microseconds to milliseconds, high emission energy is given toa low-crystallization semiconductor thin-film such aslow-crystallization silicon so that the semiconductor thin-film isheated and cooled to a fusion, a semi-fusion, or a non-fusion state, oris preferably slowly cooled, and as a result, a polycrystallinesemiconductor thin-film such as a polycrystalline silicon thin-filmhaving a large grain size, high carrier mobility, and high quality, or asingle crystalline semiconductor thin-film is obtained, whereby theproductivity rate is significantly increased, and considerable costreduction can be realized.

[0691] (2) In flash lamp annealing, by combining an optional number oflamps with a flash discharge mechanism therefor, for example, {circleover (1)} the entire large area of 1,000 mm×1,000 mm can besimultaneously irradiated once or repeatedly as required with flashemission light, {circle over (2)} flash emission light which iscondensed and homogenized to have a square emission area of 200 mm×200mm is scanned by a galvanometer scanner, and when necessary, flashemission is performed by overlap scanning, or {circle over (3)} underthe conditions in which the emission position of flash emission lightwhich is condensed and homogenized to have a square emission area of 200mm×200 mm is fixed, and a substrate is moved in a step & repeat manner,flash emission is performed and, when necessary, is performed by overlapscanning. As described above, since the substrate or flash emissionlight can be moved in an optional direction at an optional speed,heating and cooling rate can be controlled, an optional large area of alow-crystallization silicon thin-film or the like can be converted intoa polycrystalline thin-film or a single crystalline thin-film in anextremely short time, and hence, significantly high productivity andconsiderable cost reduction can be realized.

[0692] (3) Since flash emission light is condensed and homogenized tohave an optional strip, rectangular, square, or circular form and isthen emitted, the emission intensity, that is, fusion efficiency andthroughput, is improved, and variation in carrier mobility can bedecreased by improvement in uniformity of crystallization.

[0693] (4) By repeating the method in which a low-crystallizationsilicon film or the like is formed on a polycrystalline silicon film orthe like crystallized by flash lamp annealing, and crystallization isagain performed by flash lamp annealing, a polycrystalline silicon filmor the like, which has a large grain size, high carrier mobility, andhigh quality, can be formed in a laminated shape having a thickness inthe order of micrometers. Accordingly, in addition to MOSLSIs, highperformance and high quality bipolar LSIs, CMOS sensors, CCD area/linearsensors, solar cells, and the like can be formed.

[0694] (5) Since adjustment of wavelength (change of an enclosed gas,use of an IR-reducing or an IR-blocking filter, change of dischargeconditions, and the like) and control of emission intensity, emissiontime, and the like in flash lamp annealing can be easily performed inaccordance with the film thickness of a low-crystallizationsemiconductor thin-film, a heat resistant temperature of a substratesuch as glass, a desired grain size (carrier mobility), and the like, apolycrystalline silicon film or the like having high carrier mobilityand high quality can be reproducibly obtained at high productivity rate.

[0695] (6) Lamps used for flash lamp annealing, such as xenon lamps,xenon-mercury lamps, krypton lamps, krypton-mercury lamps, xenon-kryptonlamps, xenon-krypton-mercury lamps, and metal halide lamps, are muchinexpensive than an excimer laser oscillator of an excimer laserannealing apparatus using XeCl, KrF, or the like, have longer life, andrequire easier maintenance, and hence, considerable cost reduction canbe achieved.

[0696] (7) Since a flash lamp annealing apparatus primarily composed offlash lamps and a discharge circuit has a simple structure compared tothat of an excimer laser annealing apparatus, it is inexpensive, andhence, cost reduction can be realized.

[0697] (8) Since excimer laser annealing performed by XeCl, KrF, or thelike uses a pulse oscillating laser in the order of nanoseconds, therehas been a problem of output stability, and hence, there have beenvariation in energy distribution in an irradiation area, variation inquality of obtained crystallized semiconductor films, and variation inelement performance between TFTs. Accordingly, a method in which excimerlaser pulse is emitted many times, such as 5 times or 30 times, isperformed while a temperature of approximately 400° C. is applied;however, properties of crystallized semiconductor films and TFT elementsvary due to the emission variation, and the cost is increased bydecrease in productivity rate caused by decrease in throughput. Incontrast, in flash lamp annealing, as described in the above (2), sincethe entire large area of, for example, 1,000 mm×1,000 mm can besimultaneously irradiated with flash emission light using a pulse in therange of microseconds to milliseconds, variation in energy distributionin the irradiation area, variation in quality of obtained crystallizedsemiconductor films, and variation in element performance between TFTsare small, and cost reduction can be realized due to high productivityrate caused by high throughput.

[0698] (9) In particular, since flash lamp annealing by intensiveultraviolet rays, using an IR-reducing or an IR-blocking filter, can beperformed at a low temperature (200 to 400° C.), a low strain pointglass, such as aluminosilicate glass or borosilicate glass, or a heatresistant resin such as polyimide, which is inexpensive and can beformed into a large size, may be used, and hence, reduction in weightand cost can be achieve.

[0699] (10) In addition to a top gate type, since a polycrystallinesemiconductor film or a single crystalline semiconductor film havinghigh carrier mobility can be used for forming a bottom gate type, a dualgate type, and a back gate type MOSTFTs, high speed, high currentdensity semiconductor devices, electrooptic devices, and highlyefficient solar cells can be formed using this high performancesemiconductor films. For example, there may be mentioned siliconsemiconductor devices, silicon semiconductor integrated circuit devices,field emission display (FED) devices, silicon-germanium semiconductordevices, silicon-germanium semiconductor integrated circuit devices,silicon carbide semiconductor devices, silicon carbide semiconductorintegrated circuit devices, III-V and II-VI compound semiconductordevices, III-V and II-VI compound semiconductor integrated circuitdevices, polycrystalline or single crystalline diamond semiconductordevices, polycrystalline or single crystalline diamond semiconductorintegrated circuit devices, liquid crystal display devices,electroluminescent (organic or inorganic) display devices,light-emitting polymer display devices, light-emitting diode displaydevices, light sensor devices, CCD area/linear sensor devices, CMOSsensor devices, and solar cells.

1. In forming a polycrystalline or a single crystalline semiconductorthin-film on a substrate, a semiconductor thin-film forming methodcomprising: a first step of forming a low-crystallization semiconductorthin-film on the substrate; and a second step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state by flash lamp annealing to facilitate thecrystallization thereof.
 2. In forming a semiconductor device having apolycrystalline or a single crystalline semiconductor thin-film on asubstrate, a semiconductor device forming method comprising: a firststep of forming a low-crystallization semiconductor thin-film on thesubstrate; and a second step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state by flash lamp annealing to facilitate thecrystallization thereof.
 3. A method according to claim 1 or 2, whereinthe first step and the second step are repeated.
 4. A method accordingto claim 1 or 2, wherein the low-crystallization semiconductor thin-filmcontains at least one Group IV element such as tin, and the second stepis performed in this state.
 5. A method according to claim 1 or 2,wherein the low-crystallization semiconductor thin-film is convertedinto a polycrystalline semiconductor thin-film having a large grain sizeor a single crystalline semiconductor thin-film by flash lamp annealing.6. A method according to claim 1 or 2, further comprising: forming arecess portion provided with a step having a predetermined size anddimensions in a predetermined element-forming region-on the substrate;wherein the low-crystallization semiconductor thin-film, which may ormay not contain at least one Group IV element such as tin, is formed onthe substrate including the recess portion, and subsequently, performinggraphoepitaxial growth is performed using the bottom corner portion ofthe step as a seed by the flash lamp annealing so as to convert thelow-crystallization semiconductor thin-film into a single crystallinesemiconductor thin-film.
 7. A method according to claim 1 or 2, furthercomprising: forming a material layer, such as crystalline sapphire,having good lattice matching properties with a single crystallinesemiconductor in a predetermined element-forming region on thesubstrate; wherein the low-crystallization semiconductor thin-film,which may or may not contain at least one Group IV element such as tin,is formed on the material layer, and subsequently, heteroepitaxialgrowth is performed by flash lamp annealing using the material layer asa seed so as to convert the low-crystallization semiconductor thin-filminto a single crystalline semiconductor thin-film.
 8. A method accordingto claim 1 or 2, wherein the first step and the second step arecontinuously or sequentially performed in an integrated apparatus inwhich at least both steps are performed.
 9. A method according to claim3, further comprising, before the flash lamp annealing is againperformed, processing the polycrystalline semiconductor thin-film or thesingle crystalline semiconductor thin-film using hydrogen-based activespecies generated by plasma discharge or catalytic reaction of hydrogenor a hydrogen-containing gas to clean the surface of the polycrystallinesemiconductor thin-film or the single crystalline semiconductorthin-film and/or to remove an oxide film, wherein the flash lampannealing is subsequently performed after the low-crystallizationsemiconductor thin-film is formed.
 10. A method according to claim 1 or2, wherein the flash lamp annealing is performed in a hydrogenatmosphere under a reduced pressure, in a hydrogen-containing gasatmosphere under a reduced pressure, or in a vacuum.
 11. A methodaccording to claim 1 or 2, wherein the substrate is heated to a strainpoint thereof or less in the flash lamp annealing.
 12. A methodaccording to claim 1 or 2, wherein the flash lamp annealing is performedby a simultaneous flash emission in which an entire large area issimultaneously processed by at least one flash emission, a scanningemission in which flash emission is scanned at least once for the samearea, or a step and/or repeat emission in which flash emission isperformed at least once while the substrate is moved in a step and/or arepeat manner relatively with respect to the flash emission light.
 13. Amethod according to claim 1 or 2, wherein, in the flash lamp annealing,a lamp capable of withstanding repeated light emission, such as a xenonlamp, a xenon-mercury lamp, a xenon-krypton lamp, a krypton lamp, akrypton-mercury lamp, a xenon-krypton-mercury lamp, or a metal halidelamp, is used.
 14. A method according to claim 1 or 2, wherein emissionlight from a lamp used for the flash lamp annealing is controlled atleast to have a wavelength in the ultraviolet ray region, and whennecessary, the emission light is transmitted through aninfrared-reducing filter or an infrared-blocking filter, such as aninfrared-absorbing filter, an infrared-reflecting filter, or a filtercomposed of an infrared-absorbing and an infrared-reflecting filter. 15.A method according to claim 1 or 2, wherein a light-emitting apparatuscomprising an ultraviolet source and a flash discharge mechanism isused, the flash discharge mechanism optionally controlling a peak valueand a time span (pulse width) of a discharge current flowing through aflash lamp, and a repeating speed and a frequency of lamp emission inthe flash lamp annealing.
 16. A method according to claim 1 or 2,wherein a flash lamp source apparatus used for the flash lamp annealinghas at least one of the following configurations (1) to (4): (1) areflecting member is provided in a housing which contains a lamp andwhich is at the earth potential, and when necessary, minuteirregularities are formed on the surface of the reflecting member; (2) alamp and a reflecting member are provided in a housing having shadingproperties, and when necessary, flash emission light is transmittedthrough a transparent member having infrared-reducing properties orinfrared-blocking properties; (3) a lamp and a reflecting member areprovided in a housing, and flash emission light reflected and condensedand flash emission light passing in the forward direction aretransmitted through a condensing lens or a light homogenizer; and (4) areflecting member and a housing are cooled by a circulating coolant. 17.A method according to claim 1 or 2, wherein the lamp is formed as aparallel plate light-emitting tube, a pair or pairs of counterelectrodes are disposed in the light-emitting tube, and between thecounter electrodes, a trigger electrode thin-film or a trigger electrodeassembly is provided on the external wall of the light-emitting tube foreach pair of the counter electrodes.
 18. A method according to claim 1or 2, wherein pairs of counter electrodes are provided in a straightlight-emitting tube, and between the counter electrodes, a triggerelectrode thin-film or a trigger electrode assembly is provided on theexternal wall of the light-emitting tube.
 19. A method according toclaim 1 or 2, wherein a plurality of lamps is used for the flash lampannealing, the lamps are provided in parallel in plan view, and at leasttwo lamps are connected to each other in series and are connected to acorresponding power supply, each lamp is connected to a correspondingpower supply, or the plurality of lamps is connected in series and isconnected to a common power supply, whereby the plurality of lampssimultaneously emits light when being synchronously triggered.
 20. Amethod according to claim 1 or 2, wherein a flash lamp is accommodatedin a vacuum container, and a reflecting member is fixed to the vacuumcontainer with a vibration-absorbing material provided therebetween. 21.A method according to claim 1 or 2, wherein a protective, insulatingfilm is formed on the low-crystallization semiconductor thin-film, andthe flash lamp annealing is performed in this state in an air or in anitrogen atmosphere at atmospheric pressure.
 22. A method according toclaim 1 or 2, wherein, when the flash lamp annealing is performed byflash emission for the low-crystallization semiconductor thin-filmformed on the substrate or for the low-crystallization semiconductorthin-film covered with a protective, insulating film, flash emission isperformed at the top surface side, the bottom surface side, orsimultaneously at both top and bottom surface sides of the thin-film(however, when flash emission is performed at the side except the topsurface side, the substrate is transparent (which allows light having awavelength of 400 nm or less to pass therethrough).
 23. A methodaccording to claim 22, wherein islands are formed on thelow-crystallization semiconductor thin-film or on thelow-crystallization semiconductor thin-film covered with the protective,insulating film.
 24. A method according to claim 22, wherein the flashemission is performed in a nitrogen atmosphere at atmospheric pressureor in an air.
 25. A method according to claim 22, wherein the flashemission is performed in a hydrogen atmosphere under a reduced pressure,in a hydrogen-containing gas atmosphere under a reduced pressure, or ina vacuum.
 26. A method according to claim 1 or 2, wherein the flash lampannealing is performed under the influence of a magnetic field and/or anelectric field.
 27. A method according to claim 1 or 2, wherein thelow-crystallization semiconductor thin-film is formed of an amorphoussilicon film, an amorphous silicon film containing microcrystallinesilicon, a microcrystalline silicon (microcrystalline silicon containingamorphous silicon) film, a polycrystalline silicon film containingamorphous silicon and microcrystalline silicon, an amorphous germaniumfilm, an amorphous germanium film containing microcrystalline germanium,a microcrystalline germanium (microcrystalline germanium containingamorphous germanium) film, a polycrystalline germanium film containingamorphous germanium and microcrystalline germanium, an amorphous silicongermanium film represented by Si_(x)Ge_(1−x) (0<x<1), an amorphouscarbon film, an amorphous carbon film containing microcrystallinecarbon, a microcrystalline carbon (microcrystalline carbon containingamorphous carbon) film, a polycrystalline carbon film containingamorphous carbon and microcrystalline carbon, an amorphous siliconcarbide film represented by Si_(x)C_(1−x) (0<x<1⁻), an amorphous galliumarsenide film represented by Ga_(x)As_(1−x) (0<x<1), or the like.
 28. Amethod according to claim 1 or 2, wherein a channel, a source, and adrain region of a thin-film insulating gate type field effecttransistor, a diode, a wire, a resistor, a capacitor, anelectron-emitting element, or the like is formed from thepolycrystalline or the single crystalline semiconductor thin-film.
 29. Amethod according to claim 28, wherein, after the low-crystallizationsemiconductor thin-film is patterned (formation of islands) for formingthe channel, the source, and the drain regions, the diode, the resistor,the capacitor, the wire, the electron-emitting element, or the like, theflash lamp annealing is performed.
 30. A method according to claim 1 or2, wherein the thin-film is manufactured for a silicon semiconductordevice, a silicon semiconductor integrated circuit device, asilicon-germanium semiconductor device, a silicon-germaniumsemiconductor integrated circuit device, a III-V and II-VI compoundsemiconductor device, a III-V and II-VI compound semiconductorintegrated circuit device, a silicon carbide semiconductor device, asilicon carbide semiconductor integrated circuit device, apolycrystalline or a single crystalline diamond semiconductor device, apolycrystalline or a single crystalline diamond semiconductor integratedcircuit device, a liquid crystal display device, an organic or aninorganic electroluminescent (EL) device, a field emission display (FED)device, a light-emitting polymer display device, a light-emitting diodedisplay device, a CCD area/linear sensor device, a CMOS sensor device, asolar cell device, and the like.
 31. A method according to claim 30,wherein, when a semiconductor device, an electrooptic display device, asolid-state image sensing device, or the like, each having an internalcircuit and a peripheral circuit, is manufactured, a channel, a source,and a drain region of a thin-film insulating gate type field effecttransistor constituting at least one of these circuits are formed fromthe polycrystalline or the single crystalline semiconductor thin-film.32. A method according to claim 31, wherein a cathode or an anodeconnected to the drain or the source of the thin-film insulating gatetype field effect transistor is provided under each of organic orinorganic electroluminescent layers for individual colors.
 33. A methodaccording to claim 32, wherein a device is formed in which activeelements including the thin-film insulating gate type field effecttransistor and a diode are also covered with the cathode, or in whichthe cathode or the anode is provided on and between the individualorganic or inorganic electroluminescent layers for individual colors soas to cover the entire surface.
 34. A method according to claim 32,wherein a black mask layer is formed between the organic or inorganicelectroluminescent layers for individual colors.
 35. A method accordingto claim 31, wherein an emitter of a field emission display device isconnected to the drain of the thin-film insulating gate type fieldeffect transistor via the polycrystalline or the single crystallinesemiconductor thin-film and is formed from an n-type polycrystallinesemiconductor film or polycrystalline diamond film, a carbon thin-filmwhich may or may not contain nitrogen, a number of protruding structures(for example, carbon nanotube) formed on a surface of a carbon thin-filmwhich may or may not contain nitrogen, or the like, the films beingformed on the polycrystalline or the single crystalline semiconductorthin-film.
 36. A method according to claim 35, wherein a metal shieldingfilm at the earth potential is formed above active elements includingthe thin-film insulating gate type field effect transistor and a diodewith an insulating film provided therebetween.
 37. A method according toclaim 36, wherein the metal shielding film is formed of the samematerial and in the same step as those of a gate lead electrode of thefield emission display device.
 38. In an apparatus for forming apolycrystalline or a single crystalline semiconductor thin-film on asubstrate, a semiconductor thin-film forming apparatus comprising: firstmeans for forming a low-crystallization semiconductor thin-film on thesubstrate; and second means for heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state by flash lamp annealing to facilitate thecrystallization of the low-crystallization semiconductor thin-film. 39.In an apparatus for forming a semiconductor device having apolycrystalline or a single crystalline semiconductor thin-film on asubstrate, a semiconductor device forming apparatus for forming thesemiconductor device comprising: first means for forming alow-crystallization semiconductor thin-film on the substrate; and secondmeans for heating and cooling the low-crystallization semiconductorthin-film to a fusion, a semi-fusion, or a non-fusion state by flashlamp annealing to facilitate the crystallization of thelow-crystallization semiconductor thin-film.
 40. An apparatus accordingto claim 38 or 39, wherein the first means and the second means arerepeatedly used.
 41. An apparatus according to claim 38 or 39, furthercomprising means for adding at least one Group IV element such as tin atan appropriate amount to the low-crystallization semiconductorthin-film.
 42. An apparatus according to claim 38 or 39, wherein thefirst means and the second means are at least incorporated in anintegrated apparatus and are continuously or sequentially used.
 43. Anapparatus according to claim 40, further comprising, before the flashlamp annealing is again performed, means for processing thepolycrystalline semiconductor thin-film or the single crystallinesemiconductor thin-film using hydrogen-based active species generated byplasma discharge or catalytic reaction of hydrogen or ahydrogen-containing gas to clean the surface of the polycrystallinesemiconductor thin-film or the single crystalline semiconductorthin-film and/or to remove an oxide film.
 44. An apparatus according toclaim 38 or 39, wherein the flash lamp annealing is performed in ahydrogen atmosphere under a reduced pressure, in a hydrogen-containinggas atmosphere under a reduced pressure, or in a vacuum.
 45. Anapparatus according to claim 38 or 39, wherein the substrate is heatedto a strain point thereof or less in the flash lamp annealing.
 46. Anapparatus according to claim 38 or 39, wherein the flash lamp annealingis performed by a simultaneous flash emission in which an entire largearea is simultaneously processed by at least one flash emission, ascanning emission in which flash emission is scanned at least once forthe same area, or a step and/or repeat emission in which flash emissionis performed at least once while the substrate is moved in a step and/ora repeat manner relatively with respect to the flash emission light. 47.An apparatus according to claim 38 or 39, wherein, in the flash lampannealing, a lamp capable of withstanding repeated light emission, suchas a xenon lamp, a xenon-mercury lamp, a xenon-krypton lamp, a kryptonlamp, a krypton-mercury lamp, a xenon-krypton-mercury lamp, or a metalhalide lamp, is used.
 48. An apparatus according to claim 38 or 39,wherein emission light from a lamp used for the flash lamp annealing iscontrolled at least to have a wavelength in the ultraviolet ray region,and when necessary, the emission light is transmitted through aninfrared-reducing filter or an infrared blocking filter, such as aninfrared-absorbing filter, an infrared-reflecting filter, or a filtercomposed of an infrared-absorbing and an infrared-reflecting filter. 49.An apparatus according to claim 38 or 39, wherein a light-emittingapparatus comprising an ultraviolet source and a flash dischargemechanism is used, the flash discharge mechanism optionally controllinga peak value and a time span (pulse width) of a discharge currentflowing through a flash lamp, and a repeating speed and a frequency oflamp emission in the flash lamp annealing.
 50. An apparatus according toclaim 38 or 39, wherein a flash lamp source apparatus used for the flashlamp annealing has at least one of the following configurations (1) to(4): (1) a reflecting member is provided in a housing which contains alamp and which is at the earth potential, and when necessary, minuteirregularities are formed on the surface of the reflecting member; (2) alamp and a reflecting member are provided in a housing having shadingproperties, and when necessary, flash emission light is transmittedthrough a transparent member having infrared-reducing properties orinfrared-blocking properties; (3) a lamp and a reflecting member areprovided in a housing, and flash emission light reflected and condensedand flash emission light passing in the forward direction aretransmitted through a condensing lens or a light homogenizer; and (4) areflecting member and a housing are cooled by a circulating coolant. 51.An apparatus according to claim 38 or 39, wherein the lamp is formed asa parallel plate light-emitting tube, a pair or pairs of counterelectrodes are disposed in the light-emitting tube, and between thecounter electrodes, a trigger electrode thin-film or a trigger electrodeassembly is provided on the external wall of the light-emitting tube foreach pair of the counter electrodes.
 52. An apparatus according to claim38 or 39, wherein a plurality of pairs of counter electrodes is providedin a straight light-emitting tube, and between the counter electrodes, atrigger electrode thin-film or a trigger electrode assembly is providedon the external wall of the light-emitting tube.
 53. An apparatusaccording to claim 38 or 39, wherein a plurality of lamps is used forthe flash lamp annealing, the lamps are provided in parallel in planview, and at least two lamps are connected to each other in series andare connected to a corresponding power supply, each lamp is connected toa corresponding power supply, or the plurality of lamps is connected inseries and is connected to a common power supply, whereby the pluralityof lamps simultaneously emits light when being synchronously triggered.54. An apparatus according to claim 38 or 39, wherein a flash lamp isaccommodated in a vacuum container, and a reflecting member is fixed tothe vacuum container with a vibration-absorbing material providedtherebetween.
 55. An apparatus according to claim 38 or 39, wherein aprotective, insulating film is formed on the low-crystallizationsemiconductor thin-film, and the flash lamp annealing is performed inthis state in an air or in a nitrogen atmosphere at atmosphericpressure.
 56. An apparatus according to claim 38 or 39, wherein, whenthe flash lamp annealing is performed by flash emission for thelow-crystallization semiconductor thin-film formed on the substrate orfor the low-crystallization semiconductor thin-film covered with aprotective, insulating film, flash emission is performed at the topsurface side, the bottom surface side, or simultaneously at both top andbottom surface sides of the thin-film (however, when flash emission isperformed at the side except the top surface side, the substrate istransparent (which allows light having a wavelength of 400 nm or less topass therethrough).
 57. An apparatus according to claim 56, whereinislands are formed on the low-crystallization semiconductor thin-film oron the low-crystallization semiconductor thin-film covered with theprotective, insulating film.
 58. An apparatus according to claim 56,wherein the flash emission is performed in a nitrogen atmosphere atatmospheric pressure or in an air.
 59. An apparatus according to claim56, wherein the flash emission is performed in a hydrogen atmosphereunder a reduced pressure, in a hydrogen-containing gas atmosphere undera reduced pressure, or in a vacuum.
 60. An apparatus according to claim38 or 39, wherein the flash lamp annealing is performed under theinfluence of a magnetic field and/or an electric field.
 61. An apparatusaccording to claim 38 or 39, wherein the low-crystallizationsemiconductor thin-film is formed of an amorphous silicon film, anamorphous silicon film containing microcrystalline silicon, amicrocrystalline silicon (microcrystalline silicon containing amorphoussilicon) film, a polycrystalline silicon film containing amorphoussilicon and microcrystalline silicon, an amorphous germanium film, anamorphous germanium film containing microcrystalline germanium, amicrocrystalline germanium (microcrystalline germanium containingamorphous germanium) film, a polycrystalline germanium film containingamorphous germanium and microcrystalline germanium, an amorphous silicongermanium film represented by Si_(x)Ge_(1−x) (0<x<1), an amorphouscarbon film, an amorphous carbon film containing microcrystallinecarbon, a microcrystalline carbon (microcrystalline carbon containingamorphous carbon) film, a polycrystalline carbon film containingamorphous carbon and microcrystalline carbon, an amorphous siliconcarbide film represented by Si_(x)C_(1−x) (0<x<1), an amorphous galliumarsenide film represented by Ga_(x)As_(1−x) (0<x<1), or the like.
 62. Anapparatus according to Claim 38 or 39, wherein a channel, a source, anda drain region of a thin-film insulating gate type field effecttransistor, a diode, a wire, a resistor, a capacitor, anelectron-emitting element, or the like is formed from thepolycrystalline or the single crystalline semiconductor thin-film. 63.An apparatus according to claim 62, wherein, after thelow-crystallization semiconductor thin-film is patterned (formation ofislands) for forming the channel, the source, and the drain regions, thediode, the resistor, the capacitor, the wire, the electron-emittingelement, or the like, the flash lamp annealing is performed.
 64. Anapparatus according to claim 38 or 39, wherein the thin-film ismanufactured for a silicon semiconductor device, a silicon semiconductorintegrated circuit device, a silicon-germanium semiconductor device, asilicon-germanium semiconductor integrated circuit device, a III-V andII-VI compound semiconductor device, a III-V and II-VI compoundsemiconductor integrated circuit device, a silicon carbide semiconductordevice, a silicon carbide semiconductor integrated circuit device, apolycrystalline or a single crystalline diamond semiconductor device, apolycrystalline or a single crystalline diamond semiconductor integratedcircuit device, a liquid crystal display device, an organic or aninorganic electroluminescent (EL) device, a field emission display (FED)device, a light-emitting polymer display device, a light-emitting diodedisplay device, a CCD area/linear sensor device, a CMOS sensor device, asolar cell device, and the like.
 65. An apparatus according to claim 64,wherein, when a semiconductor device, an electrooptic display device, asolid-state image sensing device, or the like, each having an internalcircuit and a peripheral circuit, is formed, a channel, a source, and adrain region of a thin-film insulating gate type field effect transistorconstituting at least one of these circuits are formed of thepolycrystalline or the single crystalline semiconductor thin-film. 66.An apparatus according to claim 65, wherein a device is formed in whicha cathode or an anode connected to the drain or the source of thethin-film insulating gate type field effect transistor is provided undereach of organic or inorganic electroluminescent layers for individualcolors.
 67. An apparatus according to claim 66, wherein a device isformed in which active elements including the thin-film insulating gatetype field effect transistor and a diode are also covered with thecathode, or in which the cathode or the anode is provided on and betweenthe individual organic or inorganic electroluminescent layers forindividual colors so as to cover the entire surface.
 68. An apparatusaccording to Claim 66, wherein a black mask layer is formed between theorganic or inorganic electroluminescent layers for individual colors.69. An apparatus according to claim 65, wherein an emitter of a fieldemission display device is connected to the drain of the thin-filminsulating gate type field effect transistor via the polycrystalline orthe single crystalline semiconductor thin-film and is formed from ann-type polycrystalline semiconductor film or polycrystalline diamondfilm, a carbon thin-film which may or may not contain nitrogen, a numberof protruding structures (for example, carbon nanotube) formed on asurface of a carbon thin-film which may or may not contain nitrogen, orthe like, these films being formed on the polycrystalline or the singlecrystalline semiconductor thin-film.
 70. An apparatus according to claim69, wherein a metal shielding film at the earth potential is formedabove active elements including the thin-film insulating gate type fieldeffect transistor and a diode.
 71. An apparatus according to claim 70,wherein the metal shielding film is formed of the same material and inthe same step as those of a gate lead electrode of the field emissiondisplay device.
 72. An electrooptic device comprising: a cathode or ananode, which is provided under each of organic or inorganicelectroluminescent layers for individual colors and which is connectedto a drain or a source, which is composed of the polycrystalline or thesingle crystalline semiconductor thin-film according to claim 1 or 2, ofa thin-film insulating gate type field effect transistor; wherein activeelements including the thin-film insulating gate type field effecttransistor and a diode are also covered with the cathode, or the cathodeor the anode is provided on and between the organic or the inorganicelectroluminescent layers for individual colors so as to cover theentire surface.
 73. An electrooptic device according to claim 72,wherein a black mask layer is formed between the organic or theinorganic electroluminescent layers for individual colors.
 74. Anelectrooptic device comprising: an emitter of a field emission display(FED) device, wherein the emitter is connected to a drain, which iscomposed of the polycrystalline or the single crystalline semiconductorthin-film according to claim 1 or 2, of a thin-film insulating gate typefield effect transistor via the polycrystalline or the singlecrystalline semiconductor thin-film and is formed of an n-typepolycrystalline semiconductor film or polycrystalline diamond film, acarbon thin-film which may or may not contain nitrogen, a number ofprotruding structures (for example, carbon nanotube) formed on a surfaceof a carbon thin-film which may or may not contain nitrogen, or thelike, the films being formed on the polycrystalline or the singlecrystalline semiconductor thin-film.
 75. An electrooptic deviceaccording to claim 74, wherein a metal shielding film at the earthpotential is formed above active elements including the thin-filminsulating gate type field effect transistor and a diode with aninsulating film provided therebetween.
 76. An electrooptic deviceaccording to claim 75, wherein the metal shielding film is formed of thesame material and in the same step as those of a gate lead electrode ofthe field emission display device.
 77. A method for manufacturing asemiconductor thin-film comprising: a first step of forming alow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; asecond step of performing pre-baking in which the substrate is heated toa strain point thereof or less; a third step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state to facilitate the crystallization thereof by flashlamp annealing in assist-baking in which the substrate is heated to thestrain point thereof or less; and a fourth step of performingpost-baking in which the crystallized semiconductor thin-film is heateduntil the temperature thereof is decreased at least to the stain pointof the substrate or less.
 78. A method for manufacturing a semiconductordevice comprising: a first step of forming a low-crystallizationsemiconductor thin-film, which may or may not contain at least one GroupIV element such as tin, on a substrate; a second step of performingpre-baking in which the substrate is heated to a strain point thereof orless; a third step of heating and cooling the low-crystallizationsemiconductor thin-film to a fusion, a semi-fusion, or a non-fusionstate to facilitate the crystallization thereof by flash lamp annealingin assist-baking in which the substrate is heated to the strain pointthereof or less; and a fourth step of performing post-baking in whichthe crystallized semiconductor thin-film is heated until the temperaturethereof is decreased at least to the stain point of the substrate orless.
 79. A method according to claim 77 or 78, wherein the first step,the second step, the third step, and the fourth step are repeated.
 80. Amethod according to claim 77 or 78, wherein an appropriate emission time(⅓ pulse width) of flash lamp annealing in the pre-baking, theassist-baking, and the post-baking is 0.1 microseconds or more and ispreferably 0.5 to 3 milliseconds.
 81. A method for manufacturing anelectrooptic device comprising: patterning a low-crystallizationsemiconductor thin-film which may or may not contain at least one GroupIV element such as tin so that irradiation areas and shapes thereof inactive and passive element regions in a pixel display portion and inactive and passive element regions in a peripheral circuit portion areequivalent to each other; subsequently performing appropriate flash lampannealing of the substrate in pre-baking, assist-baking, andpost-baking; and, when necessary, patterning each crystallized region tohave a predetermined area and predetermined dimensions.
 82. A method formanufacturing an electrooptic device comprising: patterning alow-crystallization semiconductor thin-film which may or may not containat least one Group IV element such as tin so that irradiation areas andshapes thereof in active and passive element regions in a peripheralcircuit portion is larger than those in active and passive elementregions in a pixel display portion; subsequently performing appropriateflash lamp annealing of the substrate in pre-baking, assist-baking, andpost-baking; and when necessary, patterning each crystallized region tohave a predetermined area and predetermined dimensions.
 83. A method formanufacturing a semiconductor substrate or a semiconductor device,comprising; forming a recess portion in a predetermined element-formingregion of a substrate, the recess portion being provided with a stephaving a predetermined shape and predetermined dimensions, or after alaminate of an oxide-based insulating film-1, a nitride-based insulatingfilm-1, and an oxide-based insulating film-2 or a laminate of theoxide-based insulating film-1, the nitride-based insulating film-1, theoxide-based insulating film-2, and a nitride-based insulating film-2 isformed on the substrate, forming a recess portion in a predeterminedelement-forming region of the former oxide-based insulating film-2 orthe latter nitride-based insulating film-2, the recess portion beingprovided with a step having a predetermined shape and predetermineddimensions; providing a low-crystallization semiconductor thin-film,which may or may not contain at least one Group IV element such as tin,together with, when necessary, a reflection-reducing, protective,insulating film on the substrate including the recess portion; forming asingle crystalline semiconductor thin-film at least in the recessportion in accordance with graphoepitaxial growth using a bottom cornerof the step as a seed by appropriate flash lamp annealing of thesubstrate in pre-baking, assist-baking, and post-baking; processing thesurface of this single crystalline semiconductor thin-film by CMP(Chemical Mechanical Polishing: hereafter, the same as above) or byselective etching so as to form a single crystalline semiconductorthin-film having a predetermined thickness and area, the singlecrystalline semiconductor thin-film having islands formed thereon; and,when necessary, forming an SCSOS (Single Crystal Semiconductor (Silicon)On Substrate; hereafter, the same as above) substrate provided with agate insulating film or an insulating protection film formed by hightemperature thermal oxidation, low temperature and high pressureannealing, CVD (Chemical Vapor Deposition: hereafter, the same asabove), or the like.
 84. A method for manufacturing a semiconductorsubstrate or a semiconductor device, comprising; forming, whennecessary, a laminate of an oxide-based insulating film-1, anitride-based insulating film-1, and an oxide-based insulating film-2 ona substrate; forming a material layer having good lattice matchingproperties with a single crystalline semiconductor on the laminate;forming a low-crystallization semiconductor thin-film which may or maynot contain at least one Group IV element such as tin and, whennecessary, a reflection-reducing, protective, insulating film on thismaterial layer; forming a single crystalline semiconductor thin-film inaccordance with heteroepitaxial growth using this material layer as aseed by appropriate flash lamp annealing of the substrate in pre-baking,assist-baking, and post-baking; processing the surface of this singlecrystalline semiconductor thin-film by CMP or by selective etching so asto form a single crystalline semiconductor thin-film having apredetermined thickness; and, when necessary, forming an SCSOS substrateprovided with a gate insulating film or an insulating protection filmformed by high temperature thermal oxidation, low temperature and highpressure annealing, CVD, or the like.
 85. A method for manufacturing asingle crystalline semiconductor thin-film or a single crystallinesemiconductor device, comprising: forming an n-type or/and a p-typedoped region in the single crystalline semiconductor thin-film of theSCSOS substrate according to claim 83 or 84 by ion implantation or iondoping; and activating doped ions by appropriate flash lamp annealing ofthe substrate in pre-baking, assist-baking, and post-baking by using atleast an infrared-reducing or an infrared-blocking filter.
 86. A methodfor manufacturing a single crystalline semiconductor thin-film or asingle crystalline semiconductor device, comprising: forming an n-typeor/and a p-type doped region in a single crystalline semiconductorthin-film of a crystalline semiconductor substrate, such as SOI (SiliconOn Insulator) substrate, or the like, by ion implantation or ion doping;and activating doped ions by appropriate flash lamp annealing of thesubstrate in pre-baking, assist-baking, and post-baking by using atleast an infrared-reducing or an infrared-blocking filter.
 87. A methodfor manufacturing a polycrystalline or a single crystallinesemiconductor thin-film, or a polycrystalline or a single crystallinesemiconductor device, comprising: forming an n-type or/and a p-typedoped region in a polycrystalline or a single crystalline semiconductorthin-film on a substrate by ion implantation or ion doping, thecrystalline semiconductor thin-film being crystallized by laser{near-ultraviolet (UV) and/or far-ultraviolet (DUV) laser, visible lightlaser, near-infrared and/or far-infrared laser, or the like} annealing;and activating doped ions by appropriate flash lamp annealing of thesubstrate in pre-baking, assist-baking, and post-baking by using atleast an infrared-reducing or an infrared-blocking filter.
 88. A methodfor manufacturing a polycrystalline semiconductor thin-film or apolycrystalline semiconductor device, comprising: forming an n-typeor/and a p-type doped region in a polycrystalline semiconductorthin-film on a substrate by ion implantation or ion doping, thesemiconductor thin-film being crystallized by solid-phase growth; andactivating doped ions by appropriate flash lamp annealing of thesubstrate in pre-baking, assist-baking, and post-baking by using atleast an infrared-reducing or an infrared-blocking filter.
 89. A methodfor manufacturing a polycrystalline or a single crystallinesemiconductor thin-film, or a polycrystalline or a single crystallinesemiconductor device, comprising: forming an n-type or/and a p-typedoped region in a polycrystalline or a single crystalline semiconductorthin-film on a substrate by ion implantation or ion doping, thecrystalline semiconductor thin-film being crystallized by a condensinglamp annealing; and activating doped ions by appropriate flash lampannealing of the substrate in pre-baking, assist-baking, and post-bakingby using at least an infrared-reducing or an infrared-blocking filter.90. A method for manufacturing a semiconductor thin-film or asemiconductor device, comprising: a first step of forming alow-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; asecond step of forming an n-type or/and a p-type doped region in thelow-crystallization semiconductor thin-film by ion implantation or iondoping; a third step of performing pre-baking in which the substrate isheated to a strain point thereof or less; a fourth step of heating andcooling the low-crystallization semiconductor thin-film to a fusion, asemi-fusion, and a non-fusion state by flash lamp annealing inassist-baking, in which the substrate is heated to a strain pointthereof or less, to crystallize low-crystallization semiconductorthin-film and to active the dopant ions at the same time; and a fifthstep of performing post-baking in which the substrate is heated untilthe temperature thereof is decreased at least to the strain pointthereof or less.
 91. A method for manufacturing a semiconductorthin-film or a semiconductor device, comprising: a first step of forminga low-crystallization semiconductor thin-film, which may or may notcontain at least one Group IV element such as tin, on a substrate; asecond step of performing pre-baking in which the substrate is heated toa strain point thereof or less; a third step of heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,and a non-fusion state by flash lamp annealing in assist-baking in whichthe substrate is heated to the strain point thereof or less tocrystallize the low-crystallization semiconductor thin-film; a fourthstep of performing post-baking in which the substrate is heated untilthe temperature thereof is decreased to the strain point thereof orless; a fifth step of forming an n-type or/and a p-type doped region inthe formed polycrystalline or single crystalline semiconductor thin-filmby ion implantation or ion doping; and a sixth step of heating thecrystalline semiconductor thin-film in a non-fusion state by appropriateflash lamp annealing of the substrate in pre-baking, assist-baking, andpost-baking to activate the doped ions by using at least aninfrared-reducing or an infrared-blocking filter.
 92. A method formanufacturing a semiconductor thin-film or a semiconductor device,comprising: forming a shading underlying film having highly absorptiveproperties or highly reflective properties with respect to flashemission light passing through a reflection-reducing, protective,insulating film and a low-crystallization semiconductor thin-film, theunderlying film having thermal and electrical conductivities higher thanthose of the substrate; forming, when necessary, an electricalinsulating buffer film having transmission or shading properties on theunderlying film; forming a low-crystallization semiconductor thin-filmwhich may or may not contain at least one Group IV element such as tinon the buffer layer at least in the underlying film region; forming,when necessary, a reflection-reducing, protective, insulating film onthe semiconductor thin-film; and heating and cooling thelow-crystallization semiconductor thin-film to a fusion, a semi-fusion,or a non-fusion state by appropriate flash lamp annealing of thesubstrate in pre-baking, assist-baking, and post-baking to facilitatethe crystallization.
 93. A method for manufacturing a semiconductorthin-film or a semiconductor device, according to claim 92, furthercomprising: patterning the underlying film so as to have an areaequivalent to or larger than that of the low-crystallizationsemiconductor thin-film which may or may not contain at least one GroupIV element such as tin and to have a linearly protruding portion at apart of the underlying film; and dissipating heat of thelow-crystallization semiconductor thin-film in a fusion, a semi-fusion,or a non-fusion state by flash lamp annealing from the protrudingportion of the underlying film to form nuclei for crystal growth,whereby the entire thin-film is crystallized in an optional crystalorientation.
 94. A method for manufacturing a semiconductor thin-film ora semiconductor device, according to claim 92, further comprising:patterning the low-crystallization semiconductor thin-film which may ormay not contain at least one Group IV element such as tin so as to havean area equivalent to or smaller than that of the underlying film and tohave a minute projecting portion in a protruding portion region of theunderlying film; and dissipating heat of the low-crystallizationsemiconductor thin-film in a fusion, a semi-fusion, or a non-fusionstate by flash lamp annealing from the minute projecting portion on theunderlying film to form nuclei for crystal growth, whereby the entirethin-film is crystallized in an optional crystal orientation.
 95. Amethod for manufacturing a semiconductor thin-film or a semiconductordevice, according to one of claims 92 to 94, wherein the underlying filmis used at an optional potential via the linearly protruding portion.96. A method for manufacturing a semiconductor thin-film or asemiconductor device, according to claim 92, wherein thereflection-reducing, protective film used in the flash lamp annealing isan electrical insulating film which allows at least ultraviolet rays topass therethrough and may be used as a gate insulating film in somecases.
 97. A method for manufacturing a semiconductor thin-film or asemiconductor device, comprising: when a low-crystallizationsemiconductor thin-film which may or may not contain at least one GroupIV element such as tin is crystallized while being heated to cooled to afusion or a semi-fusion state by flash lamp annealing in an oxidizingatmosphere, simultaneously forming an oxide-based insulating film on asurface of this low-crystallization or the crystallized singlecrystalline semiconductor thin-film, wherein the oxide-based insulatingfilm is used as a gate insulating film or a protection film.
 98. Amethod for manufacturing a semiconductor thin-film or a semiconductor,device, comprising: on a polycrystalline or a single crystallinesemiconductor thin-film, which may or may not contain at least one GroupIV element such as tin and which is formed by flash lamp annealing on alow strain point glass, a high strain point glass, or a resin substrate,forming an oxide-based insulating film at a high pressure in the rangeof 0.1 MPa to 30 MPa and at a low temperature in the range of roomtemperature to a strain point of the substrate in an oxidizingatmosphere, wherein the oxide-based insulating film is used as a gateinsulating film or a protection film.
 99. A method for manufacturing asemiconductor thin-film or a semiconductor device, comprising: formingan oxide-based insulating film by high temperature thermal oxidation inan oxidizing atmosphere of a polycrystalline or a single crystallinesemiconductor thin-film, which may or may not contain at least one GroupIV element such as tin and which is formed by flash lamp annealing on ahigh strain point glass substrate, wherein the oxide-based insulatingfilm is used as a gate insulating film or a protection film.
 100. Amethod for manufacturing a semiconductor thin-film or a semiconductordevice, comprising: forming an oxide-based insulating film by hightemperature thermal oxidation in an oxidizing atmosphere of apolycrystalline or a single crystalline semiconductor thin-film, whichmay or may not contain at least one Group IV element such as tin, isprovided with a reflection-reducing, protective, insulating film, and isformed by flash lamp annealing on a high strain point glass substrate,wherein the oxide-based insulating film is used as a gate insulatingfilm or a protection film.
 101. A method for manufacturing asemiconductor thin-film or a semiconductor device, comprising: modifyingat least one of an insulating film and a polycrystalline or a singlecrystalline semiconductor thin-film, which is formed by flash lampannealing and which may or may not contain at least one Group IV elementsuch as tin, by a heating step (steam annealing) performed in anatmosphere containing water vapor at a partial pressure of 13.33 Pa tothe saturated vapor pressure and at a temperature in the range of roomtemperature to a strain point of a substrate.